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PRELIMINARY
CY14B108L, CY14B108N
Document #: 001-45523 Rev. *B Page 6 of 24
Table 2. Mode Selection
CE WE OE, BHE, BLE
[3]
A
15
- A
0
[5]
Mode IO Power
H X X X Not Selected Output High Z Standby
L H L X Read SRAM Output Data Active
L L X X Write SRAM Input Data Active
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Disable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[6]
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
[6]
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active I
CC2
[6]
L H L 0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
[6]
Notes
5. While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A
14
- A
2
) are used to control software modes.
Rest of the address lines are don’t care.
6. The six consecutive address locations must be in the order listed. WE
must be HIGH during all six cycles to enable a nonvolatile cycle.
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