PRELIMINARY
CY14B108L, CY14B108N
Document #: 001-45523 Rev. *B Page 3 of 24
Table 1. Pin Definitions
Pin Name I/O Type Description
A
0
– A
19
Input Address Inputs Used to Select one of the 1,048,576 bytes of the nvSRAM for x8 Configuration.
A
0
– A
18
Address Inputs Used to Select one of the 524,288 words of the nvSRAM for x16 Configuration.
DQ
0
– DQ
7
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
operation.
DQ
0
– DQ
15
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
operation.
WE Input Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific
address location.
CE
Input Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
OE
Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE
HIGH.
BHE
Input Byte High Enable, Active LOW. Controls DQ
15
- DQ
8
.
BLE
Input Byte Low Enable, Active LOW. Controls DQ
7
- DQ
0
.
V
SS
Ground Ground for the Device. Must be connected to the ground of the system.
V
CC
Power Supply Power Supply Inputs to the Device.
HSB
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in
progress. When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak
internal pull up resistor keeps this pin HIGH if not connected (connection optional). After each STORE
operation HSB
will be driven HIGH for short time with standard output high current.
V
CAP
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC No Connect No Connect. This pin is not connected to the die.
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