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STK12C68
Document Number: 001-51027 Rev. ** Page 12 of 20
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows.
[18]
Parameter Alt Description
25 ns 35 ns 45 ns
Unit
Min Max Min Max Min Max
t
RC
[14]
t
AVAV
STORE/RECALL Initiation Cycle Time 25 35 45 ns
t
SA
[17]
t
AVEL
Address Setup Time 0 0 0 ns
t
CW
[17]
t
ELEH
Clock Pulse Width 20 25 30 ns
t
HACE
[17]
t
ELAX
Address Hold Time 20 20 20 ns
t
RECALL
RECALL Duration 20 20 20
μ
s
Switching Waveform
Figure 12. CE Controlled Software STORE/RECALL Cycle
[18]
t
RC
t
RC
t
SA
t
SCE
t
HACE
t
STORE
/ t
RECALL
DATA VALID
DATA VALID
6#SSERDDA1#SSERDDA
HIGH IMPEDANCE
ADDRESS
CE
OE
DQ (DATA)
Notes
17.The software sequence is clocked on the falling edge of CE
without involving OE (double clocking aborts the sequence).
18.The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE
must be HIGH during all six consecutive cycles.
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