PMC-Sierra PM5349 Manual

A SERVICE OF

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S/UNI-QUAD

PMC-Sierra, Inc.

PM5349 S/UNI-QUAD

DATASHEET

PMC-971239 ISSUE 6 SATURN USER NETWORK INTERFACE (155-QUAD)

Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use

10

No line rate clocks are required directly by the S/UNI-QUAD as it synthesizes the

transmit clock and recovers the receive clock using a 19.44 MHz reference clock.

The S/UNI-QUAD outputs a differential TTL (externally coverted to PECL) line

data (TXD+/-).

The S/UNI-QUAD is configured, controlled and monitored via a generic 8-bit

microprocessor bus interface. The S/UNI-QUAD also provides a standard 5

signal IEEE 1149.1 JTAG test port for boundary scan board test purposes.

The S/UNI-QUAD is implemented in low power, +3.3 Volt, CMOS technology. It

has TTL and pseudo-ECL (PECL) compatible inputs and TTL/CMOS compatible

outputs and is packaged in a 304 pin SBGA package.