4.9InterruptMaskSetRegister(IMSR)
DDR2MemoryControllerRegisters
Theinterruptmasksetregister(IMSR)enablestheDDR2memorycontrollerinterrupt.TheIMSRisshown
inFigure27anddescribedinTable33.
Note:IftheLTMSETbitinIMSRissetconcurrentlywiththeLTMCLRbitintheinterruptmaskclear
register(IMCR),theinterruptisnotenabledandneitherbitissetto1.
Figure27.InterruptMaskSetRegister(IMSR)
3116
Reserved
R-0
153210
ReservedLTMSETReserved
R-0R/W-0R-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table33.InterruptMaskSetRegister(IMSR)FieldDescriptions
BitFieldValueDescription
31-3Reserved0Reserved
2LTMSETLinetrapinterruptset.Writea1tosetLTMSETandtheLTMCLRbitintheinterruptmaskclearregister
(IMCR);awriteof0hasnoeffect.
0Linetrapinterruptisnotenabled;awriteof1totheLTMCLRbitinIMCRoccurred.
1Linetrapinterruptisenabled.
1-0Reserved0Reserved
50DDR2MemoryControllerSPRU986B–November2007
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