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Dell PowerEdge M910 Technical Guide 25
8 Chipset
The PowerEdge M910 system board incorporates the Intel
®
7500 chipset for I/O and processor
interfacing. The 7500 chipset is designed to support Intel
®
Xeon
®
processor 6500 and 7500 series 4S
family, Intel
®
QPI Interconnect, DDR3 memory technology, and PCI Express Generation 2 (PCIe 2).
The 7500 chipset consists of the IOH QuickPath Interconnect (QPI), Intel
®
7500 Scalable Memory
Buffer, and the ICH10 South Bridge.
8.1 Intel 7500 I/O Hub (IOH)
The PowerEdge M910 system board incorporates an Intel 7500 series IOH to provide a link between
the 4S processors and the I/O components. The main components of the IOH consist of two full‐width
QPI links (one to each processor), 36 lanes of PCIe Gen2, and a x4 DMI link to connect directly to the
ICH10 (Intel I/O Controller Hub 10) South Bridge.
8.2 IOH QuickPath Interconnect (QPI)
The QPI architecture consists of serial point‐to‐point interconnects for the processors and the IOH.
The PowerEdge M910 has a total of four QPI links including one link connecting the processors and
links connecting both processors with the IOH. Each link consists of 20 lanes (full‐width) in each
direction with a link speed of 6.4 GT/s. An additional lane is reserved for a forwarded clock. Data is
sent over the QPI links as packets.
The QPI architecture features the following four layers:
The Physical layer consists of the actual connection between components. It supports Polarity
Inversion and Lane Reversal for optimizing component placement and routing.
The Link layer is responsible for flow control and the reliable transmission of data.
The Routing layer is responsible for the routing of QPI data packets.
Finally, the Protocol layer is responsible for high‐level protocol communications, including
the implementation of a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence
protocol.
8.3 PCI EXPRESS GENERATION 2
PCI Express (PCIe) is a serial point‐to‐point interconnect for I/O devices. PCIe Gen2 doubles the
signaling bit rate of each lane from 2.5 Gb/s to 5 Gb/s. Each of the PCIe Gen2 ports is backward‐
compatible with Gen1 transfer rates.
8.4 Direct Media Interface (DMI)
The DMI (previously called the Enterprise Southbridge Interface) connects the Intel 7500 Legacy IOH
with the Intel I/O Controller Hub (ICH). The DMI is equivalent to a x4 PCIe Gen1 link with a transfer
rate of 1 GB/s in each direction.
8.5 Intel I/O Controller Hub 10 (ICH10)
ICH10 is a highly integrated I/O controller, supporting the following functions:
• Six x1 PCIe Gen1 ports, with the capability of combining ports 1‐4 as a x4 link
• PCI Bus 32‐bit Interface Rev 2.3 running at 33 MHz
• Six UHCI and two EHCI (High‐Speed 2.0) USB host controllers, with up to twelve USB ports