24888 Rev 3.03 - July 12, 2004 AMD-8151
TM
AGP Tunnel Data Sheet
31
AGP Bridge Bus Numbers And Secondary Latency Register DevB:0x18
Default: 0000 0000h Attribute: Read-write.
AGP Bridge Memory Base-Limit Registers DevB:0x[30:1C]
These registers specify the IO-space (DevB:0x1C and DevB:0x30), non-prefetchable memory-space
(DevB:0x20), and prefetchable memory-space (DevB:0x24) address windows for transactions that are mapped
from the 40-bit link address space to the AGP bus.
The links support 25 bits of IO space. AGP supports 32 bits of IO space. Host accesses to the link-defined IO
region are mapped to the AGP IO window with the 7 MSB always zero. AGP IO accesses in which any of the
7 MSBs are other than zero are ignored. The AGP IO space window is defined as follow:
AGP IO window =
{7'h00, DevB:30[24:16], DevB:0x1C[15:12], 12'hFFF} >= address >=
{7'h00, DevB:30[8:0], DevB:0x1C[7:4], 12'h000};
The links support 40 bits of memory space. AGP supports 32 bits of non-prefetchable memory space. The AGP
non-prefetchable window is defined to be within the lowest 4 gigabytes of link address space. AGP accesses
above 4 gigabytes cannot access non-prefetchable memory space. The AGP non-prefetchable memory space
window is defined as follows:
AGP non-prefetchable memory window =
{32'h00, DevB:0x20[31:20], 20'hF_FFFF} >= address >=
{32'h00, DevB:0x20[15:4], 20'h0_0000};
The links support 40 bits of memory space. AGP supports 32 bits of prefetchable memory space. The AGP
prefetchable window is defined to be within the lowest 4 gigabytes of link address space. The AGP prefetch-
able memory space window is defined as follows:
AGP prefetchable memory window =
{32'h00, DevB:0x24[31:20], 20'hF_FFFF} >= address >=
{32'h00, DevB:0x24[15:4], 20'h0_0000};
These windows may also be altered by DevB:0x3C[VGAEN, ISAEN]. When the address (from either the host
or from an AGP bus master) is inside one of the windows, then the transaction targets the AGP bus. Therefore,
the following transactions are possible:
15:8 LATENCY. Read-write. These bits control no hardware.
7:0 CACHE. Read only. These bits fixed at their default values.
Bits Description
31:24 SECLAT. Secondary latency timer. These bits control no hardware.
23:16 SUBBUS. Subordinate bus number.
15:8 SECBUS. Secondary bus number.
7:0 PRIBUS. Primary bus number.
