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4-2-7 APC CIRCUIT (MAIN UNIT)
The APC circuit protects the power amplifier from a mis-
matched output load and stabilizes the output power.
The APC detector circuit (D14, D17, L39) detects forward
signals and reflection signals at D14 and D17 respectively.
The combined voltage is at minimum level when the anten-
na impedance is matched at 50 Ω and is increased when it
is mismatched.
The detected voltage is applied to the differential amplifier
(IC6, pin 2), and the power setting voltage is applied to the
other input (pin 1) for the reference.
When antenna impedance is mismatched, the detected volt-
age exceeds the power setting voltage. The output voltage
of the differential amplifier (IC6, pin 1) controls the input cur-
rent of the power module (IC10) to reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and the receive 1st LO frequency. The PLL circuit
compares the phase of the divided VCO frequency to the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of a programmable divider.
An oscillated signal from the VCO passes thorough the LO
and buffer amplifiers (Q9, Q12) is applied to the PLL IC (IC1,
pin 6) and is prescaled in the PLL IC based on the divided
ratio (N-data). The reference signal is generated at the ref-
erence oscillator (X1) and is also applied to the PLL IC. The
PLL IC detects the out-of-step phase using the reference
frequency and outputs it from pin 15. The output signal is
passed through the loop filter (Q2, R6, R11–R15, C11, C12)
and is then applied to the VCO circuit as the lock voltage via
the “LV” line.
4-3-2 VCO CIRCUIT (MAIN unit)
The VCO circuit contains a separate TX-VCO (Q6, D2, D4)
and RX-VCO (Q7, D5, D38). The oscillated signal is ampli-
fied at the LO (Q9) and buffer (Q11) amplifiers, and is then
applied to the T/R switching circuit (D6, D7). Then the Tx
and Rx signals are applied to the pre-driver (Q17) and 1st
mixer (Q19) respectively.
A portion of the signal from Q4 is amplified at the buffer
amplifier (Q6) and is then fed back to the PLL IC (IC1 pin 2)
as the comparison signal.
Power
amp.
IC6
APC
amp.
Driver
amp.
+
—
Pre
drive
HV
to the antenna
T1
TXC
IC11
Q26, Q39, Q40
RF signal
T8
APC control circuit
Q17
Q35
IC10
Power detector circuit
L39
D14 D17
• APC CIRCUIT
Shift register
Prescaler
Phase
detector
Charge
pump
Loop
filter
Programmable
divider
Reference
divider
X1
21.25 MHz
1
LO
Buffer
Buffer
2
3
4
PLLCK
PLLDATA
PLLSTB
to transmitter circuit
to 1st mixer circuit
D6
D7
Q11
Q12
Q9
9
6
Q6, D2, D4
TX VCO
Q7, D5
RX VCO
IC1 LV2105V
21.25 MHz 2nd LO signal
to the FM IF IC (IC4, pin 2)
16
LPF
LPF
• PLL CIRCUIT
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