Vector Floating-point Programming
6-34 Copyright © 2000, 2001 ARM Limited. All rights reserved. ARM DUI 0068B
6.7.15 FMUL and FNMUL
Floating-point multiply and negate-multiply.
FMUL
and
FNMUL
can be scalar, vector, or
mixed (see Vector and scalar operations on page 6-7).
Syntax
FMUL<precision>{cond} Fd, Fn, Fm
FNMUL<precision>{cond} Fd, Fn, Fm
where:
<precision>
must be either
S
for single-precision, or
D
for double-precision.
cond
is an optional condition code (see VFP and condition codes on page 6-8).
Fd
is the VFP register for the result.
Fn
is the VFP register holding the first operand.
Fm
is the VFP register holding the second operand.
The precision of
Fd
,
Fn
and
Fm
must match the precision specified in
<precision>
.
Usage
The
FMUL
instruction multiplies the values in
Fn
and
Fm
and places the result in
Fd
.
The
FNMUL
instruction multiplies the values in
Fn
and
Fm
and places the negation of the
result in
Fd
.
Exceptions
FMUL
and
FNMUL
operations can produce Invalid Operation, Overflow, Underflow, or
Inexact exceptions.
Examples
FNMULS s10, s10, s14
FMULDLT d0, d7, d8
