Scan IF Registers
24-50 Scan IF
SIFTSMx, Scan IF Timing State Machine Registers
15 14 13 12 11 10 9 8
SIFREPEATx SIFACLK SIFSTOP SIFDAC
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
76543210
SIFTESTS1 SIFRSON SIFCLKON SIFCA SIFEX SIFLCEN SIFCHx
rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)
SIF
REPEATx
Bits
15-11
These bits together with the SIFACLK bit configure the duration of this state.
SIFREPEATx selects the number of clock cycles for this state. The number
of clock cycles = SIFREPEATx + 1.
SIFACLK
Bit 10 This bit selects the clock source for the TSM.
0 The TSM clock source is the high frequency source selected by the
SIFCLKEN bit.
1 The TSM clock source is ACLK
SIFSTOP
Bit 9 This bit indicates the end of the TSM sequence. The duration of this state is
always one high-frequency clock period, regardless of the SIFACLK and
SIFREPEATx settings.
0 TSM sequence continues with next state
1 End of TSM sequence
SIFDAC
Bit 8 TSM DAC on. This bit turns the DAC on during this state when SIFDACON
= 0.
0 DAC off during this state.
1 DAC on during this state.
SIFTESTS1
Bit 7 TSM test cycle control. This bit selects for this state which channel-control bits
and which DAC registers are used for a test cycle.
0 The SIFTCH0x bits select the channel and SIFDACR6 is used for the
DAC
1 The SIFTCH1x bits select the channel and SIFDACR7 is used for the
DAC
SIFRSON
Bit 6 Internal output latches enabled. This bit enables the internal latches of the
AFE output stage.
0 Output latches disabled
1 Output latches enabled
