Hardware Description
3-4
© Copyright ARM Limited 1999. All rights reserved.
ARM DUI 0125A
3.3 Core module FPGA
The core module FPGA contains five main functional blocks:
• SDRAM controller on page 3-6
• Reset controller on page 3-8
• System bus bridge on page 3-11
• Core module registers on page 4-7
• Debug interrupt controller, see Debug communications interrupts on page 3-27.
The FPGA provides sufficient functionality for the core module to operate as a
standalone development system, although with limited capabilities. System bus
arbitration, system interrupt control, and input/output resources are provided by the
system controller FPGA on the motherboard. See the user guide for your motherboard
for further information.
Figure 3-1 illustrates the function of the core module FPGA and shows how it connects
to the other devices in the system.
Figure 3-1 FPGA functional diagram
FPGA
SDRAM
SSRAM
ARM core
SSRAM
controller
(PLD)
SDRAM
controller
System bus connectors
HDRA/HDRB
Multi-ICE
Clock
generator
Memory bus
System bus
Status/
control
registers
Reset
controller
System bus
bridge
