Hardware Description
ARM DUI 0125A
© Copyright ARM Limited 1999. All rights reserved.
3-19
3.7.2 Processor bus clocks (LCLK and nLCLK)
The frequency of the processor bus clocks LCLK and nLCLK is determined by the
frequency of 2XCLK. The clock signal 2XCLK is divided by 2 by the SSRAM
controller PLD to produce LCLK and nLCLK.
The frequency of LCLK is controllable in 0.5MHz steps in the range 6MHz to 66MHz.
This is achieved by programming the VCO and output divider bits for the 2XCLK
generator in the CM_OSC register. The VCO divider is controlled by the L_VDW bits
and the output divider is controlled by the L_OD bits.The reference divider is fixed.
The maximum speed of 2XCLK is limited by the speed of the SSRAM PLD.
Table 3-3 shows the values placed on the divider input pins and how the clock speeds
are obtained. The bits marked:
• L are programmable in the CM_OSC register
• 1 are tied HIGH
• 0 are tied LOW
.
The frequency of LCLK can be derived from the formula:
freq = (L_VDW+ 8)/L_OD
where:
L_VDW is the VCO divider word for the processor bus clock.
L_OD is the output divider for the processor bus clock.
Note
Values for L_VDW and L_OD can be calculated using the ICS525 calculator on the
Microclock website.
For details about programming L_VDW and L_OD, see CM_OSC (0x10000008) on
page 4-9.
Table 3-3 2XCLK divider values
L_RDW R[6:0] L_VDW V[8:0] L_OD S[2:0]
00101100LLLLLLLLLLL
22 (fixed value) 4 – 124 (<4 and >124 not allowed) 2-10
12 – 132MHz in 1MHz steps (for 2XCLK)
