GL815E Endura Motherboard Product Manual
Page 39 of 51
Address (hex)* Description
FFA0 – FFA7 Primary IDE bus master registers
FFA8 – FFAF Secondary IDE bus master registers
Dynamically assigned USB controller (32 locations on 32-byte boundary)
Dynamically assigned SMBus controller ("6 locations on "6-byte boundary)
Dynamically assigned PCI bridge (4096 locations on a 4096-byte boundary)
Dynamically assigned LAN controller (32 locations on a 32-byte boundary)
* An ‘x’ prefix for the address indicates that only the low-order "0 address bits are decoded.
A.2. PCI Interrupt Allocation
In order to share PCI interrupts efficiently, the routing of the PCI interrupts INTA - INTD to the
motherboard PCI interrupts PIRQA – PIRQD are rotated for each slot. Thus the PCI card INTA
signal for PCI slots " to 4 are spread across all four motherboard inputs. The Ethernet controller
and the second USB channel use additional motherboard PCI interrupts (PIRQE and PIRQH) that
are not routed to the slots. Interrupts PIRQF and PIRQG are not used and not available to the slots.
Device PIRQA PIRQB PIRQC PIRQD PIRQE PIRQH
Slot " (AGP4X) INTA INTB - - - -
Slot 2 (PCI 2.2) INTD INTA INTB INTC - -
Slot 3 (PCI 2.2) INTC INTD INTA INTB - -
Slot 4 (PCI 2.2) INTB INTC INTD INTA - -
Slot 5 (PCI 2.2) INTA INTB INTC INTD - -
Slot 6 (PCI 2.2) INTD INTA INTB INTC - -
VGA controller INTA - - - - -
Ethernet controller - - - - INTA -
USB controller " ---INTD--
USB controller 2 - - - - - INTC
SMBus controller - INTB - - - -
AC97 audio controller - INTB - - - -
Example. From the table above, the INTA interrupt from a card plugged into slot 2 would be routed
to the motherboard PIRQB.
