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2.0 Functional Description
2.4 Channel Unit Interface
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
Parallel slave mode uses RBCLK and TBCLK inputs to synchronize data
transfer. RBCLK and TBCLK must be frequency-locked to QCLK, though the
use of two internal FIFOs allow an arbitrary phase relationship to QCLK. TQ[1]
and TQ[0] are sampled on the active edge of TBCLK, as programmed through the
MCI. RQ[1] and RQ[0] are output on the active edge of RBCLK, also as pro-
grammed through the MCI. The clock relationships for the case where TBCLK is
programmed to be falling-edge active and RBCLK is rising-edge active are illus-
trated in Figure 2-8.
Figure 2-8. Parallel Slave Mode
TBCLK
Sign
0
Sign
2
Sign
1
Magnitude
0
Magnitude
1
Magnitude
2
TQ[1]
TQ[0]
RBCLK
Sign
0
Sign
2
Sign
1
Magnitude
0
Magnitude
1
Magnitude
2
RQ[1]
RQ[0]