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4.0 Electrical & Mechanical Specifications
4.6 Microcomputer Interface Timing
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
4.6 Microcomputer Interface Timing
Table 4-13. Microcomputer Interface Timing Requirements
Symbol Parameter Minimum Maximum Units
34 ALE Pulse-Width High 30 ns
35
Address Setup prior to ALE Falling Edge
(1)
12 ns
36
Address Hold after ALE Low
(1)
5 ns
37
ALE low prior to Write Strobe
Falling Edge
(2)
20 ns
38
ALE low prior to Read Strobe
Falling Edge
(3,4)
–27 ns
39
Write Strobe
Pulse-Width Low
(2,5)
2*Tmclk +25 ns
40
Read Strobe
Pulse-Width Low
(3,5)
2*Tmclk +25 ns
41
Data In Setup prior to Write Strobe
Rising Edge
(2)
30 ns
42
Data In Hold after Write Strobe
High
(2)
5 ns
43 R/W
Setup prior to Read/Write Strobe Falling Edge 10 ns
44 R/W Hold after Read/Write Strobe High 10 ns
45 ALE Falling Edge after Write Strobe High 20 ns
46 ALE Falling Edge after Read Strobe High 20 ns
47 RST Pulse-Width Low 50 ns
48 Write Strobe Rising Edge after READY low 0 ns
Notes: (1). Address is defined as AD[7:0] when MUXED = 1, and ADDR[7:0] when MUXED = 0.
(2). In Intel mode, Write Strobe
is defined as WR and CS asserted. In Motorola mode, it is defined as DS and CS asserted
when R/W
is low.
(3). In Intel mode, Read Strobe
is defined as RD and CS asserted. In Motorola mode, it is defined as DS and CS asserted
when R/W
is high.
(4). Parameter 38 is –27 ns only if separate address and data busses are used (i.e., muxed = 0). If muxed = 1, then parameter
38 is 20 ns.
(5). The timing listed is for the synchronous mode of the MCI. It can also be set to synchronous mode by setting bit 0 of the
reserved2 register (address 0x0F) to a 1. In this case the minimum timing changes to 40 us for symbol 39, and 50 us
for symbols 40 and 50. Synchronous mode is preferred because it reduces internal switching noise, however no signif-
icant performance degradation has been measured as a result of using the asynchronous mode.
