45
3.0 Registers
3.1 Conventions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
smon[5:0] Serial Monitor Source Select—Read/write binary field selects the Serial Monitor (SMON) out-
put source.
3.2.3 0x02—Interrupt Mask Register Low (mask_low_reg)
Independent read/write mask bits for each of the Timer Source Register [timer_source; 0x04] interrupt flags. A
logic one represents the masked condition. A logic zero represents the unmasked condition. All mask bits
behave identically with respect to their corresponding interrupt flags. Setting a mask bit prevents the corre-
sponding interrupt flag from affecting the IRQ
output. Clearing a mask allows the interrupt flag to affect IRQ
output. Unmasking an active interrupt flag will immediately cause the IRQ output to go active, if currently inac-
tive. Masking an active interrupt flag will cause IRQ
to go inactive, if no other unmasked interrupt flags are set.
t4 General Purpose Timer 4
t3 General Purpose Timer 3
snr SNR Alarm Timer
meter Meter Timer
sut4 Startup Timer 4
sut3 Startup Timer 3
sut2 Startup Timer 2
sut1 Startup Timer 1
smon[5:0]
Source
Decimal Binary
0 – 47 00 0000 – 10 1111 Equalizer Register File
48 11 0000 Digital Front-End Output/LEC Input
49 11 0001 Linear Echo Replica
50 11 0010 DFE Subtactor Output/EP Input
51 11 0011 EP Subtractor Output/Slicer Input
52 11 0100 Timing Recovery Phase Detector Output/Loop Filter Input
53 11 0101 Timing Recovery Loop Filter Output/Frequency Synthesizer Input
7 6 5 4 3 2 1 0
t4 t3 snr meter su4 sut3 sut2 sut1
