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3.0 Registers
3.1 Conventions
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
3.2.6 0x05—IRQ Source Register (irq_source)
Independent read/write (zero only) interrupt flags, one for each of four internal sources. Each flag bit is set and
stays set when its corresponding source indicates that a valid interrupt condition exists. If unmasked, this event
will cause the IRQ
output to be activated. Writing a logic zero to an interrupt flag whose underlying condition
no longer exists will cause the flag to be immediately cleared. Attempting to clear a flag whose underlying con-
dition still exists will not immediately clear the flag, but will allow it to remain set until the underlying condition
expires, at which time the flag will be cleared automatically. The clearing of an unmasked flag will cause the
IRQ
output to return to an inactive state, if no other unmasked interrupt flags are set.
sync Sync Indication—Active when the sync detector is enabled and its accumulated equivalent
comparisons exceeds (greater than) the threshold value stored in the Scrambler Sync Thresh-
old Register [scr_sync_th; 0x2E].
high_felm Far-End Level Meter High Alarm—Active when the far-end level meter value exceeds (greater
than) the threshold stored in the Far-End High Alarm Threshold Registers
[far_end_high_alarm_th_low, far_end_high_alarm_th_high; 0x30–0x31].
low_felm Far-End Level Meter Low Alarm—Active when the far-end level meter value exceeds (less
than) the threshold stored in the Far-End Low Alarm Threshold Registers
[far_end_low_alarm_th_low, far_end_low_alarm_th_high; 0x32–0x33].
low_snr Signal-to-Noise Ratio Low Alarm—Active when the SNR Alarm meter value exceeds (greater
than) the threshold stored in the SNR Alarm Threshold Registers [snr_alarm_th_low,
snr_alarm_th_high; 0x34–0x35].
3.2.7 0x06—Channel Unit Interface Modes Register (cu_interface_modes)
tbclk_pol Transmit Baud Clock Polarity—Read/write control bit defines the polarity of the TBCLK
input while in the parallel slave interface mode. When set, TQ[1,0] is sampled on the falling
edge of TBCLK; when cleared, TQ[1,0] is sampled on the rising edge.
rbclk_pol Receive Baud Clock Polarity—Read/write control bit defines the polarity of the RBCLK input
while in the parallel slave interface mode. When set, RQ[1,0] is updated on the falling edge of
RBCLK; when cleared, RQ[1,0] is updated on the rising edge.
fifos_mode FIFO’s Mode—Read/write control bit used to stagger the transmit and receive FIFO’s read and
write pointers while in the parallel slave interface mode. A logic one forces the pointers to a
staggered position, while a logic zero allows them to operate normally. Must be first set, then
cleared once after QCLK-TBCLK-RBCLK frequency lock is achieved to maximize phase-
error tolerance.
interface_
mode[1,0]
Interface Mode—Read/write binary field specifies one of four operating modes for the channel
unit interface.
7 6 5 4 3 2 1 0
– – – – sync high_felm low_felm low_snr
7 6 5 4 3 2 1 0
– – – tbclk_pol rbclk_pol fifos_mode interface_mode[1] interface_mode[0]
