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4.0 Electrical & Mechanical Specifications
4.4 Clock Timing
Bt8960
Single-Chip 2B1Q Transceiver
N8960DSB
Table 4-6. Symbol Clock (QCLK) Switching Characteristics
Symbol Parameter Minimum Maximum Units
9
QCLK Period (T
QCLK
)
(1)
K x T
HCLK
K x T
HCLK
10 QCLK Pulse-Width High T
QCLK
÷ 2 –
20
T
QCLK
÷ 2 +
20
ns
11 QCLK Pulse-Width Low T
QCLK
÷ 2 –
20
T
QCLK
÷ 2 +
20
ns
12 QCLK Hold after HCLK Rising Edge –20
13 QCLK Delay after HCLK High 20
Note: (1). K = 16, 32 or 64 according to hclk_freq[1,0]. QCLK can be frequency locked to the incoming data symbol rate.
Figure 4-2. Clock Control Timing
4,5,6
11
10
9
7
8
12
13
HCLK
QCLK