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Evaluation Board for Quad T1/E1 Applications — LXD386
Developer Manual 25
Figure 14. Evaluation Board Schematic — Digital I/O
DIGITAL I/O A4
FIREBIRD - LXD386 DEMO BOARD
B
66Wednesday, September 15, 1999
Title
Size Document Number Rev
Date: Sheet
of
RNEG1/BPV1
RPOS1/RDATA1
RCLK1
RNEG0/BPV0
RPOS0/RDATA0
RCLK0
TCLK1
TPOS1/TDATA1
TCLK2
RCLK3
RNEG2/BPV2
TPOS3/TDATA3
RNEG3/BPV3
TPOS2/TDATA2
RCLK2
RPOS2/RDATA2
TCLK3
RPOS3/RDATA3
TNEG0/UBS0
TNEG1/UBS1
TNEG2/UBS2
TNEG3/UBS3
TCLK0
TPOS0/TDATA0
LOS0
LOS1
LOS2
LOS3
JP16
HEADER 5X2
12
34
56
78
910
JP15
HEADER 5X2
12
34
56
78
910
JP17
HEADER 5X2
12
34
56
78
910
JP18
HEADER 5X2
12
34
56
78
910
R61
100k
R62
100k
R60
100k
R64
100k
R65
100k
R63
100k
R67
100k
R68
100k
R66
100k
R70
100k
R71
100k
R69
100k
LEVEL ONE COMMUNICATIONS
CHANNEL 1
CHANNEL 0
CHANNEL 2
CHANNEL 3