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Hardware Description
3-92 Copyright © 2003-2007 ARM Limited. All rights reserved. ARM DUI 0224F
3.21 USB interface
The FPGA provides the bus interface to an external OTG243 USB controller. Three
USB interfaces are provided on the PB926EJ-S, see Figure 3-41.
The internal registers of the controller are memory-mapped onto the AHB M2 bus at
0x10020000
.
Figure 3-41 OTG243 block diagram
OTG243 USB port 1 provides an OTG device interface and connects to J6. OTG243
USB ports 2 and 3 can function in either master or slave mode and connect to the dual
type A connector J7 (USB2 is the top connector).