1.4IndustryStandard(s)ComplianceStatement
2Architecture
2.1ClockControl
2.1.1MIIClocking
2.1.2GMIIClocking
Architecture
TheEMACandMDIOinterruptsarecombinedwithinthecontrolmodule,soonlythecontrolmodule
interruptneedstobemonitoredbytheapplicationsoftwareordevicedriver.TheEMACcontrolmodule
combinestheEMACandMDIOinterruptsandgenerates4separateinterruptstotheARMthroughthe
ARMinterruptcontroller.SeeSection2.16.4fordetailsofinterruptmultiplexlogicoftheEMACcontrol
module.
TheEMACperipheralconformstotheIEEE802.3standard,describingtheCarrierSenseMultipleAccess
withCollisionDetection(CSMA/CD)AccessMethodandPhysicalLayerspecifications.TheIEEE802.3
standardhasalsobeenadoptedbyISO/IECandre-designatedasISO/IEC8802-3:2000(E).
Indifferencefromthisstandard,theEMACperipheraldoesnotusetheTransmitCodingErrorsignal
MTXER.Insteadofdrivingtheerrorpinwhenanunderflowconditionoccursonatransmittedframe,the
EMACintentionallygeneratesanincorrectchecksumbyinvertingtheframeCRC,sothatthetransmitted
frameisdetectedasanerrorbythenetwork.
ThissectiondiscussesthearchitectureandbasicfunctionoftheEMAC/MDIOmodule.
ThefrequenciesforthetransmitandreceiveclocksarefixedbytheIEEE802.3specificationas:
•2.5MHZat10Mbps
•25MHZat100Mbps
•125MHZat1000Mbps
AllEMAClogicisclockedsynchronouslywiththePLLperipheralclock.TheMDIOclockcanbecontrolled
throughtheapplicationsoftware,byprogrammingthedivide-downfactorintheMDIOcontrolregister
(CONTROL).
Inthe10/100Mbpsmode,thetransmitandreceiveclocksourcesareprovidedfromanexternalPHYvia
theMTCLKandMRCLKpins.TheseclocksareinputstotheEMACmoduleandoperateat2.5MHZin10
Mbpsmodeandat25MHZin100Mbpsmode.TheMIIclockinginterfaceisnotusedin1000Mbps
mode.Fortimingpurposes,dataistransmittedandreceivedwithreferencetoMTCLKandMRCLK,
respectively.
Inthe1000Mbpsmode,thetransmitandreceiveclocksourcesfor10/100Mbpsoperationareprovided
fromanexternalPHYviatheMTCLKandMRCLKpins,asintheMIIclocking.For1000Mbpsoperation,
thereceiveclockisprovidedbyanexternalPHYviatheMRCLKpin.Fortransmitin1000Mbpsmode,the
clockissourcedsynchronouswiththedataandisprovidedbytheEMACtobeoutputontheGMTCLK
pin.
TheEMACmoduleisinternallyclockedat148.5MHZ.Fortimingpurposes,datain10/100Mbpsmodeis
transmittedandreceivedwithreferencetoMTCLKandMRCLK,respectively.For1000Mbpsmode,
receivetimingisthesame,buttransmitisrelativetoGMTCLK.
EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO) 14SPRUEQ6–December2007
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