2.15.3MDIOModuleInitialization
Architecture
TheMDIOmoduleisusedtoinitiallyconfigureandmonitoroneormoreexternalPHYdevices.Other
thaninitializingthesoftwarestatemachine(detailsonthisstatemachinecanbefoundinthe
IEEE802.3standard),allthatneedstobedonefortheMDIOmoduleistoenabletheMDIOengine
andtoconfiguretheclockdivider.Tosettheclockdivider,supplyanMDIOclockof1MHZ.For
example,sincethebaseclockusedistheperipheralclock(PLL1/6),foraprocessoroperatingataPLL
frequencyof594MHZthedividercanbesetto99,withslowerMDIOclocksforslowerperipheralclock
frequenciesbeingperfectlyacceptable.
BoththestatemachineenableandtheMDIOclockdividerarecontrolledthroughtheMDIOcontrol
register(CONTROL).IfnoneofthepotentiallyconnectedPHYsrequiretheaccesspreamble,the
PREAMBLEbitinCONTROLcanalsobesettospeedupPHYregisteraccess.Thecodeforthismay
appearasinExample5.
Example5.MDIOModuleInitializationCode
#definePCLK99
...
/*EnableMDIOandsetupdivider*/
MDIO_REGS->CONTROL=CSL_FMKT(MDIO_CONTROL_ENABLE,YES)|
CSL_FMK(MDIO_CONTROL_CLKDIV,PCLK);
IftheMDIOmoduleistooperateonaninterruptbasis,theinterruptscanbeenabledatthistimeusing
theMDIOusercommandcompleteinterruptmasksetregister(USERINTMASKSET)forregisteraccess
andtheMDIOuserPHYselectregister(USERPHYSELn)ifatargetPHYisalreadyknown.
OncetheMDIOstatemachinehasbeeninitializedandenabled,itstartspollingall32PHYaddresses
ontheMDIObus,lookingforanactivePHY.Sinceitcantakeupto50µstoreadoneregister,itcan
besometimebeforetheMDIOmoduleprovidesanaccuraterepresentationofwhetheraPHYis
available.Also,aPHYcantakeupto3secondstonegotiatealink.Thus,itisadvisabletorunthe
MDIOsoftwareoffatime-basedeventratherthanpolling.
FormoreinformationonPHYcontrolregisters,seeyourPHYdevicedocumentation.
54EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)SPRUEQ6–December2007
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