2.16.2MDIOModuleInterruptEventsandRequests
2.16.2.1LinkChangeInterrupt
2.16.2.2UserAccessCompletionInterrupt
2.16.3ProperInterruptProcessing
2.16.4InterruptMultiplexing
Architecture
TheMDIOmodulegeneratestwointerruptevents:
•LINKINT:Serialinterfacelinkchangeinterrupt.IndicatesachangeinthestateofthePHYlink
•USERINT:Serialinterfaceusercommandeventcompleteinterrupt
TheMDIOmoduleassertsalinkchangeinterrupt(LINKINT)ifthereisachangeinthelinkstateofthe
PHYcorrespondingtotheaddressinthePHYADRMONbitintheMDIOuserPHYselectregistern
(USERPHYSELn),andiftheLINKINTENBbitisalsosetinUSERPHYSELn.Thisinterrupteventisalso
capturedintheLINKINTRAWbitintheMDIOlinkstatuschangeinterruptregister(LINKINTRAW).
LINKINTRAWbits0and1correspondtoUSERPHYSEL0andUSERPHYSEL1,respectively.
Whentheinterruptisenabledandgenerated,thecorrespondingLINKINTMASKEDbitisalsosetinthe
MDIOlinkstatuschangeinterruptregister(LINKINTMASKED).Theinterruptisclearedbywritingback
thesamebittoLINKINTMASKED(writetoclear).
WhentheGObitinoneoftheMDIOuseraccessregisters(USERACCESSn)transitionsfrom1to0
(indicatingcompletionofauseraccess)andthecorrespondingUSERINTMASKSETbitintheMDIO
usercommandcompleteinterruptmasksetregister(USERINTMASKSET)correspondingto
USERACCESS0orUSERACCESS1isset,auseraccesscompletioninterrupt(USERINT)isasserted.
ThisinterrupteventisalsocapturedintheUSERINTRAWbitintheMDIOusercommandcomplete
interruptregister(USERINTRAW).USERINTRAWbits0andbit1correspondtoUSERACCESS0and
USERACCESS1,respectively.
Whentheinterruptisenabledandgenerated,thecorrespondingUSERINTMASKEDbitisalsosetin
theMDIOusercommandcompleteinterruptregister(USERINTMASKED).Theinterruptisclearedby
writingbackthesamebittoUSERINTMASKED(writetoclear).
AlltheinterruptssignaledfromtheEMACandMDIOmodulesareleveldriven,soiftheyremainactive,
theirlevelremainsconstant;theCPUcorerequiresedge-triggeredinterrupts.Inordertoproperly
convertthelevel-driveninterruptsignaltoanedge-triggeredsignal,theapplicationsoftwaremustmake
useoftheinterruptcontrollogiccontainedintheEMACcontrolmodule.
Section2.6.3discussestheinterruptcontrolcontainedintheEMACcontrolmodule.Forsafeinterrupt
processing,uponentrytotheISR,thesoftwareapplicationshoulddisableinterruptsusingtheEMAC
controlmoduleinterruptcontrolregisters(CMRXTHRESHINTEN,CMRXINTEN,CMTXINTEN,and
CMMISCINTEN),andthenreenablethemuponleavingtheISR.Ifanyinterruptsignalsareactiveat
thattime,thiscreatesanotherrisingedgeontheinterruptsignalgoingtotheCPUinterruptcontroller,
thustriggeringanotherinterrupt.TheEMACcontrolmodulealsoimplementstheoptionalinterrupt
pacing.
TheEMACcontrolmodulecombinesallthedifferentinterruptsignalsfromboththeEMACandMDIO
modulesandgeneratesfourseparateinterruptsignals(Table5)thatarewiredtotheARMinterrupt
controller(AINTC),asseeninFigure12.Oncethisinterruptisgenerated,thereasonfortheinterrupt
canbereadfromtheMACinputvectorregister(MACINVECTOR)locatedintheEMACmemorymap.
MACINVECTORcombinesthestatusofthefollowing28interruptsignals:TXPENDn,RXPENDn,
RXTHRESHPENDn,STATPEND,HOSTPEND,LINKINT,andUSERINT.
FormoredetailsontheARMinterruptcontroller(AINTC),seetheTMS320DM646xDMSoCARM
SubsystemReferenceGuide(SPRUEP9).
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)59
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