2.7.2.4ExampleofMDIORegisterAccessCode
Architecture
TheMDIOmoduleusestheMDIOuseraccessregister(USERACCESSn)toaccessthePHYcontrol
registers.Softwarefunctionsthatimplementtheaccessprocessmaysimplybethefollowingfourmacros:
StarttheprocessofreadingaPHYregister
•PHYREG_read(regadr,phyadr)
StarttheprocessofwritingaPHYregister
•PHYREG_write(regadr,phyadr,data)
Synchronizeoperation(makesureread/writeisidle)
•PHYREG_wait()
Waitforreadtocompleteandreturndataread
•PHYREG_waitResults(results)
Notethatitisnotnecessarytowaitafterawriteoperation,aslongasthestatusischeckedbeforeevery
operationtomakesuretheMDIOhardwareisidle.AnalternativeapproachistocallPHYREG_wait()after
everywrite,andPHYREG_waitResults()aftereveryread,thenthehardwarecanbeassumedtobeidle
whenstartinganewoperation.
Theimplementationofthesemacrosusingthechipsupportlibrary(CSL)isshowninExample3
(USERACCESS0isassumed).
NotethatthisimplementationdoesnotchecktheACKbitinUSERACCESSnonPHYregisterreads(does
notfollowtheprocedureoutlinedinSection2.7.2.3).SincetheMDIOPHYalivestatusregister(ALIVE)is
usedtoinitiallyselectaPHY,itisassumedthatthePHYisacknowledgingreadoperations.Itispossible
thataPHYcouldbecomeinactiveatafuturepointintime.AnexampleofthiswouldbeaPHYthatcan
haveitsMDIOaddresseschangedwhilethesystemisrunning.Itisnotverylikely,butthisconditioncan
betestedbyperiodicallycheckingthePHYstateinALIVE.
Example3.MDIORegisterAccessMacros
#definePHYREG_read(regadr,phyadr)
MDIO_REGS->USERACCESS0=
CSL_FMK(MDIO_USERACCESS0_GO,1u)|/
CSL_FMK(MDIO_USERACCESS0_REGADR,regadr)|/
CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr)
#definePHYREG_write(regadr,phyadr,data)
MDIO_REGS->USERACCESS0=
CSL_FMK(MDIO_USERACCESS0_GO,1u)|/
CSL_FMK(MDIO_USERACCESS0_WRITE,1)|/
CSL_FMK(MDIO_USERACCESS0_REGADR,regadr)|/
CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr)|/
CSL_FMK(MDIO_USERACCESS0_DATA,data)
#definePHYREG_wait()
while(CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO))
#definePHYREG_waitResults(results){
while(CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO));
results=CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_DATA);}
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)37
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