2.6.3.3ReceiveThresholdPulseInterrupt
2.6.3.4MiscellaneousPulseInterrupt
2.6.4InterruptPacing
Architecture
TheEMACcontrolmodulereceivestheeightindividualreceivethresholdinterruptsoriginatingfromthe
EMACmodule,oneforeachoftheeightchannels,andcombinesthemintoasinglereceivethreshold
pulseinterrupttotheCPU.Thisreceivethresholdpulseinterruptisnotpaced.Theeightindividualreceive
thresholdpendinginterrupt(s)areselectedattheEMACcontrolmodulelevel,bysettingoneormorebits
intheEMACcontrolmodulereceivethresholdinterruptenableregister(CMRXTHRESHINTEN).The
maskedinterruptstatuscanbereadintheEMACcontrolmodulereceivethresholdinterruptstatus
register(CMRXTHRESHINTSTAT).
Uponreceptionofareceivethresholdpulseinterrupt,theISRperformsthefollowing:
1.ReadCMRXTHRESHINTSTATtodeterminewhichchannel(s)causedtheinterrupt.
2.Processreceivedpacketsinordertoaddmorebufferstoanychannelthatisbelowthethreshold
value.
3.WritetheappropriateCPGMACreceivechannelncompletionpointerregister(s)(RXnCP)withthe
addressofthelastbufferdescriptorofthelastpacketprocessedbytheapplicationsoftware.
4.WritetheMACendofinterruptvectorregister(MACEOIVECTOR)intheEMACmodulewithavalueof
0tosignaltheendofthereceivethresholdinterruptprocessing.
TheEMACcontrolmodulereceivestheSTATPENDandHOSTPENDinterruptsfromtheEMACmodule
andtheMDIO_LINKINTandMDIO_USERINTinterruptsfromtheMDIOmodule.TheEMACcontrol
modulecombinesthesefourinterruptsintoasinglemiscellaneouspulseinterrupttotheCPU.This
miscellaneousinterruptisnotpaced.ThefourindividualinterruptsareselectedattheEMACcontrol
modulelevel,bysettingoneormorebitsintheEMACcontrolmodulemiscellaneousinterruptenable
register(CMMISCINTEN).ThemaskedinterruptstatuscanbereadintheEMACcontrolmodule
miscellaneousinterruptstatusregister(CMMISCINTSTAT).
Uponreceptionofamiscellaneouspulseinterrupt,theISRperformsthefollowing:
1.ReadCMMISCINTSTATtodeterminewhichofthefourcondition(s)causedtheinterrupt.
2.Processthoseinterruptsaccordingly.
3.WritetheMACendofinterruptvectorregister(MACEOIVECTOR)intheEMACmodulewithavalueof
3htosignaltheendofthemiscellaneousinterruptprocessing.
Thereceiveandtransmitpulseinterruptscanbepaced.Thereceivethresholdandmiscellaneous
interruptscannotbepaced.TheinterruptpacingfeaturelimitsthenumberofinterruptstotheCPUduring
agivenperiodoftime.Forheavilyloadedsystemsinwhichinterruptscanoccurataveryhighrate,the
performancebenefitissignificantduetominimizingtheoverheadassociatedwithservicingeachinterrupt.
Thereceiveandtransmitpulseinterruptscontainaseparateinterruptpacingsub-blocks.Eachsub-block
isdisabledbydefaultallowingtheselectedinterruptinputstopass-throughunaffected.
Theinterruptpacingmodulecountsthenumberofinterruptsthatoccurovera1msintervaloftime.Atthe
endofeach1msinterval,thecurrentnumberofinterruptsiscomparedwithatargetnumberofinterrupts
(specifiedbytheassociatedEMACcontrolmoduleinterruptspermillisecondregisters,CMTXINTMAXand
CMRXINTMAX).Basedontheresultsofthecomparison,thelengthoftimeduringwhichinterruptsare
blockedisdynamicallyadjusted.The1msintervalisderivedfroma4µspulsethatiscreatedfroma
prescalecounterwhosevalueissetintheINTPRESCALEfieldoftheEMACcontrolmoduleinterrupt
controlregister(CMINTCTRL).ThisINTPRESCALEvalueshouldbewrittenwiththenumberofperipheral
clockperiodsin4µs.Thepacingtimerdeterminestheintervalduringwhichinterruptsareblockedand
decrementsevery4µs.Itisreloadedeachtimeazerocountisreached.Thevalueloadedintothepacing
timeriscalculatedbyhardwareevery1ms,accordingtothedynamicalgorithminthehardware.
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)33
SubmitDocumentationFeedback
