5.9TransmitInterruptMaskSetRegister(TXINTMASKSET)
EthernetMediaAccessController(EMAC)Registers
Thetransmitinterruptmasksetregister(TXINTMASKSET)isshowninFigure49anddescribedin
Table48.
Figure49.TransmitInterruptMaskSetRegister(TXINTMASKSET)
3116
Reserved
R-0
158
Reserved
R-0
76543210
TX7MASKTX6MASKTX5MASKTX4MASKTX3MASKTX2MASKTX1MASKTX0MASK
R/W1S-0R/W1S-0R/W1S-0R/W1S-0R/W1S-0R/W1S-0R/W1S-0R/W1S-0
LEGEND:R=Readonly;R/W=Read/Write;W1S=Write1toset,writeof0hasnoeffect;-n=valueafterreset
Table48.TransmitInterruptMaskSetRegister(TXINTMASKSET)FieldDescriptions
BitFieldValueDescription
31-8Reserved0Reserved
7TX7MASK0-1Transmitchannel7interruptmasksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
6TX6MASK0-1Transmitchannel6interruptmasksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
5TX5MASK0-1Transmitchannel5interruptmasksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
4TX4MASK0-1Transmitchannel4interruptmasksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
3TX3MASK0-1Transmitchannel3interruptmasksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
2TX2MASK0-1Transmitchannel2interruptmasksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
1TX1MASK0-1Transmitchannel1interruptmasksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
0TX0MASK0-1Transmitchannel0interruptmasksetbit.Write1toenableinterrupt,awriteof0hasnoeffect.
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)93
SubmitDocumentationFeedback
