3.9EMACControlModuleReceiveThresholdInterruptStatusRegister
3.10EMACControlModuleReceiveInterruptStatusRegister(CMRXINTSTAT)
EMACControlModuleRegisters
(CMRXTHRESHINTSTAT)
Thereceivethresholdinterruptstatusregister(CMRXTHRESHINTSTAT)isshowninFigure21and
describedinTable18.
Figure21.EMACControlModuleReceiveThresholdInterruptStatusRegister
(CMRXTHRESHINTSTAT)
3116
Reserved
R-0
15870
ReservedRXTHRESHINTTSTAT
R-0R-0
LEGEND:R=Readonly;-n=valueafterreset
Table18.EMACControlModuleReceiveThresholdInterruptStatusRegister
(CMRXTHRESHINTSTAT)FieldDescriptions
BitFieldValueDescription
31-8Reserved0Reserved
7-0RXTHRESHINTTSTAT[n]Receivethresholdinterruptstatus.Eachbitshowsthestatusofthecorresponding
channelnreceivethresholdinterrupt.
Bitn=0,channelnreceivethresholdinterruptisnotpending.
Bitn=1,channelnreceivethresholdinterruptispending.
Thereceiveinterruptstatusregister(CMRXINTSTAT)isshowninFigure22anddescribedinTable19.
Figure22.EMACControlModuleReceiveInterruptStatusRegister(CMRXINTSTAT)
3116
Reserved
R-0
15870
ReservedRXPULSEINTTSTAT
R-0R-0
LEGEND:R=Readonly;-n=valueafterreset
Table19.EMACControlModuleReceiveInterruptStatusRegister(CMRXINTSTAT)
FieldDescriptions
BitFieldValueDescription
31-8Reserved0Reserved
7-0RXPULSEINTTSTAT[n]Receiveinterruptstatus.Eachbitshowsthestatusofthecorrespondingchannelnreceive
interrupt.
Bitn=0,channelnreceiveinterruptisnotpending.
Bitn=1,channelnreceiveinterruptispending.
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)67
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