2.2MemoryMap
2.3SignalDescriptions
2.3.1MediaIndependentInterface(MII)Connections
MTCLK
MTXD(7−0)
MTXEN
MCOL
MCRS
MRCLK
MRXD(7−0)
MRXDV
MRXER
MDCLK
MDIO
Physical
layer
device
(PHY)
System
core
Transformer
2.5 MHz,
25 MHz or
125 MHz
RJ−45
EMACMDIO
Architecture
TheEMACperipheralincludesinternalmemorythatisusedtoholdinformationabouttheEthernet
packetsreceivedandtransmitted.ThisinternalRAMis2K×32bitsinsize.Datacanbewrittentoand
readfromtheEMACinternalmemorybyeithertheEMACortheCPU.Itisusedtostorebufferdescriptors
thatare4-words(16-bytes)deep.This8Klocalmemoryholdsenoughinformationtotransferupto512
EthernetpacketswithoutCPUintervention.
Thepacketbufferdescriptorscanalsobeplacedintheinternalprocessormemory(L2),orinEMIF
memory(DDR).Therearesometradeoffsintermsofcacheperformanceandthroughputwhen
descriptorsareplacedinthesystemmemory,versuswhentheyareplacedintheEMAC’sinternal
memory.Cacheperformanceisimprovedwhenthebufferdescriptorsareplacedininternalmemory.
However,theEMACthroughputisbetterwhenthedescriptorsareplacedinthelocalEMACRAM.
TheDM646xDMSoCsupportsbothMIIinterface(for10/100Mbpsoperation)andGMIIinterface(for
10/100/1000Mbps)operation.
Figure2showsadevicewithintegratedEMACandMDIOinterfacedviaaMIIconnection.TheEMAC
moduledoesnotincludeatransmiterror(MTXER)pin.Inthecaseoftransmiterror,CRCinversionis
usedtonegatethevalidityofthetransmittedframe.
TheindividualEMACandMDIOsignalsfortheMIIinterfacearesummarizedinTable1.Formore
information,refertoeithertheIEEE802.3standardorISO/IEC8802-3:2000(E).
Figure2.EthernetConfiguration—MIIConnections
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)15
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