2.8.1.3MACReceiver
2.8.1.4ReceiveAddress
2.8.1.5TransmitDMAEngine
2.8.1.6TransmitFIFO
2.8.1.7MACTransmitter
2.8.1.8StatisticsLogic
2.8.1.9StateRAM
2.8.1.10EMACInterruptController
2.8.1.11ControlRegistersandLogic
2.8.1.12ClockandResetLogic
Architecture
TheMACreceiverdetectsandprocessesincomingnetworkframes,de-framesthem,andputstheminto
thereceiveFIFO.TheMACreceiveralsodetectserrorsandpassesstatisticstothestatisticsRAM.
Thissub-moduleperformsaddressmatchingandaddressfilteringbasedontheincomingpacket’s
destinationaddress.Itcontainsa32-by-53bittwo-portRAM,inwhichupto32addressescanbestoredto
beeithermatchedorfilteredbytheEMAC.TheRAMmaycontainmulticastpacketaddresses,butthe
associatedchannelmusthavetheunicastenablebitset,eventhoughitisamulticastaddress.The
unicastenablebitsareusedwithmulticastaddressesinthereceiveaddressRAM(notthemulticasthash
enablebits).Therefore,hashmatchescanbedisabled,butspecificmulticastaddressescanbematched
(orfiltered)intheRAM.Ifamulticastpackethashmatches,thepacketmaystillbefilteredintheRAM.
Eachpacketcanbesenttoonlyasinglechannel.
ThetransmitDMAengineistheinterfacebetweenthetransmitFIFOandtheCPU.Itinterfacestothe
CPUthroughthebusarbiterintheEMACcontrolmodule.
ThetransmitFIFOconsistsof24cellsof64byteseachandassociatedcontrollogic.Thisenablesa
packetof1518bytes(standardEthernetpacketsize)tobesentwithoutthepossibilityofunderrun.The
FIFObuffersdatainpreparationfortransmission.
TheMACtransmitterformatsframedatafromthetransmitFIFOandtransmitsthedatausingthe
CSMA/CDaccessprotocol.TheframeCRCcanbeautomaticallyappended,ifrequired.TheMAC
transmitteralsodetectstransmissionerrorsandpassesstatisticstothestatisticsregisters.
TheEthernetstatisticsarecountedandstoredinthestatisticslogicRAM.ThisstatisticsRAMkeepstrack
of36differentEthernetpacketstatistics.
StateRAMcontainstheheaddescriptorpointersandcompletionpointersregistersforbothtransmitand
receivechannels.
Theinterruptcontrollercontainstheinterruptrelatedregistersandlogic.The18rawEMACinterruptsare
inputtothissubmoduleandmaskedmoduleinterruptsareoutput.
TheEMACiscontrolledbyasetofmemory-mappedregisters.Thecontrollogicalsosignalstransmit,
receive,andstatusrelatedinterruptstotheCPUthroughtheEMACcontrolmodule.
TheclockandresetsubmodulegeneratesalltheEMACclocksandresets.Formoredetailsonreset
capabilities,seeSection2.14.1.
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)39
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