2.15.4EMACModuleInitialization
Architecture
TheEMACmoduleisusedtosendandreceivedatapacketsoverthenetwork.Thisisdoneby
maintaininguptoeighttransmitandreceivedescriptorqueues.TheEMACmoduleconfigurationmust
alsobekeptup-to-datebasedonPHYnegotiationresultsreturnedfromtheMDIOmodule.Mostofthe
workindevelopinganapplicationordevicedriverforEthernetisprogrammingthismodule.
ThefollowingistheinitializationprocedureadevicedriverwouldfollowtogettheEMACtothestate
whereitisreadytoreceiveandsendEthernetpackets.Someofthesestepsarenotnecessarywhen
performedimmediatelyafterdevicereset.
1.ProgramtheVDD3P3V_PWDNregisterintheSystemmoduletopoweruptheCPGMACI/Ocells
(seethedevice-specificdatamanual).ThereareseparatecontrolsforMIII/OpinsandGMIII/O
pins,whicharepowereddownbydefaultatsystemreset,tosavepower.
2.Ifenabled,clearthedeviceinterruptenableintheEMACcontrolmoduleinterruptcontrolregisters
(CMRXTHRESHINTEN,CMRXINTEN,CMTXINTEN,andCMMISCINTEN).
3.CleartheMACcontrolregister(MACCONTROL),receivecontrolregister(RXCONTROL),and
transmitcontrolregister(TXCONTROL)(notnecessaryimmediatelyafterreset).
4.Initializeall16headerdescriptorpointerregisters(RXnHDPandTXnHDP)to0.
5.Clearall36statisticsregistersbywriting0(notnecessaryimmediatelyafterreset).
6.SetupthelocalEthernetMACaddressbyprogrammingtheMACindexregister(MACINDEX),MAC
addresshighbytesregister(MACADDRHI),andMACaddresslowbytesregister(MACADDRLO).
BesuretoprogramalleightMACaddresses-whetherthereceivechannelistobeenabledornot.
DuplicatethesameMACaddressacrossallunusedchannels.Whenusingmorethanonereceive
channel,startwithchannel0andprogressupwards.
7.Initializethereceivechannelnfreebuffercountregisters(RXnFREEBUFFER),receivechanneln
flowcontrolthresholdregister(RXnFLOWTHRESH),andreceivefilterlowpriorityframethreshold
register(RXFILTERLOWTHRESH),ifbufferflowcontrolistobeenabled.
8.Mostdevicedriversopenwithnomulticastaddresses,socleartheMACaddresshashregisters
(MACHASH1andMACHASH2)to0.
9.Writethereceivebufferoffsetregister(RXBUFFEROFFSET)value(typicallyzero).
10.InitiallyclearallunicastchannelsbywritingFFhtothereceiveunicastclearregister
(RXUNICASTCLEAR).Ifunicastisdesired,itcanbeenablednowbywritingthereceiveunicastset
register(RXUNICASTSET).Somedriverswilldefaulttounicastondeviceopenwhileotherswillnot.
11.Setupthereceivemulticast/broadcast/promiscuouschannelenableregister(RXMBPENABLE)with
aninitialconfiguration.Theconfigurationisbasedonthecurrentreceivefiltersettingsofthedevice
driver.Somedriversmayenablethingslikebroadcastandmulticastpacketsimmediately,while
othersmaynot.
12.SettheappropriateconfigurationbitsinMACCONTROL(donotsettheGMIIENbityet).
13.Clearallunusedchannelinterruptbitsbywritingthereceiveinterruptmaskclearregister
(RXINTMASKCLEAR)andthetransmitinterruptmaskclearregister(TXINTMASKCLEAR).
14.Enablethereceiveandtransmitchannelinterruptbitsinthereceiveinterruptmasksetregister
(RXINTMASKSET)andthetransmitinterruptmasksetregister(TXINTMASKSET)forthechannels
tobeused,andenabletheHOSTMASKandSTATMASKbitsusingtheMACinterruptmaskset
register(MACINTMASKSET).
15.Initializethereceiveandtransmitdescriptorlistqueues.
16.PreparereceivebywritingapointertotheheadofthereceivebufferdescriptorlisttoRXnHDP.
17.EnablethereceiveandtransmitDMAcontrollersbysettingtheRXENbitinRXCONTROLandthe
TXENbitinTXCONTROL.ThensettheGMIIENbitinMACCONTROL.
18.EnablethedeviceinterruptintheEMACcontrolmoduleinterruptcontrolregisters
(CMRXTHRESHINTEN,CMRXINTEN,CMTXINTEN,andCMMISCINTEN).
SPRUEQ6–December2007EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO)55
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