2.6.3InterruptControl
2.6.3.1TransmitPulseInterrupt
2.6.3.2ReceivePulseInterrupt
Architecture
TheEMACcontrolmodulecombinesmultipleinterruptconditionsgeneratedbytheEMACandMDIO
modulesintofourseparateinterruptsignals(Table5)thataremappedtoaCPUinterruptviatheCPU
interruptcontroller.Thefourseparatesourcesofinterruptcanbeindividuallyenabledforeachchannelby
theCMRXTHRESHINTEN,CMRXINTEN,CMTXINTEN,andCMMISCINTENregisters.
Table5.EMACControlModuleInterrupts
ARMEventAcronymSource
24MAC_RXTHEMACreceivethreshold
25MAC_RXEMACreceive
26MAC_TXEMACtransmit
27MAC_MISCEMACmiscellaneous
TheEMACcontrolmodulereceivestheeightindividualtransmitinterruptsoriginatingfromtheEMAC
module,oneforeachoftheeightchannels,andcombinesthemintoasingletransmitpulseinterruptto
theCPU.Thistransmitpulseinterruptispaced,asdescribedinSection2.6.4.Theeightindividual
transmitpendinginterrupt(s)areselectedattheEMACcontrolmodulelevel,bysettingoneormorebitsin
theEMACcontrolmoduletransmitinterruptenableregister(CMTXINTEN).Themaskedinterruptstatus
canbereadintheEMACcontrolmoduletransmitinterruptstatusregister(CMTXINTSTAT).
Uponreceptionofatransmitpulseinterrupt,theISRperformsthefollowing:
1.ReadCMTXINTSTATtodeterminewhichchannel(s)causedtheinterrupt.
2.Processreceivedpacketsfortheinterruptingchannel(s).
3.WritetheappropriateCPGMACtransmitchannelncompletionpointerregister(s)(TXnCP)withthe
addressofthelastbufferdescriptorofthelastpacketprocessedbytheapplicationsoftware.
4.WritetheMACendofinterruptvectorregister(MACEOIVECTOR)intheEMACmodulewithavalueof
2htosignaltheendofthetransmitinterruptprocessing.
TheEMACcontrolmodulereceivestheeightindividualreceiveinterruptsoriginatingfromtheEMAC
module,oneforeachoftheeightchannels,andcombinesthemintoasinglereceivepulseinterrupttothe
CPU.Thisreceivepulseinterruptispaced,asdescribedinSection2.6.4.Theeightindividualreceive
pendinginterrupt(s)areselectedattheEMACcontrolmodulelevel,bysettingoneormorebitsinthe
EMACcontrolmodulereceiveinterruptenableregister(CMRXINTEN).Themaskedinterruptstatuscan
bereadintheEMACcontrolmodulereceiveinterruptstatusregister(CMRXINTSTAT).
Uponreceptionofareceivepulseinterrupt,theISRperformsthefollowing:
1.ReadCMRXINTSTATtodeterminewhichchannel(s)causedtheinterrupt.
2.Processreceivedpacketsfortheinterruptingchannel(s).
3.WritetheappropriateCPGMACreceivechannelncompletionpointerregister(s)(RXnCP)withthe
addressofthelastbufferdescriptorofthelastpacketprocessedbytheapplicationsoftware.
4.WritetheMACendofinterruptvectorregister(MACEOIVECTOR)intheEMACmodulewithavalueof
1htosignaltheendofthereceiveinterruptprocessing.
EthernetMediaAccessController(EMAC)/ManagementDataInput/Output(MDIO) 32SPRUEQ6–December2007
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