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2004 Jan 26 43
Philips Semiconductors Product specification
MPEG-2 video and MPEG-audio/AC-3
audio encoder with multiplexer
SAA6752HS
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45 I horizontal shift R/W 2 bytes 0 to 511 (bits 0 to 8) 0 (D1,
2
/
3
D1)
or
8(
1
/
2
D1, SIF)
defines the number of shifted cycles for
every line; remark: 4 cycles correspond to
2 pixels; only multiple of 4 should be
programmed
46 I sync polarity R/W byte 000 defines the polarity of the sync signals
bit 0 = 0 H-sync signal HIGH for
horizontal blanking
bit 0 = 1 H-sync signal LOW for
horizontal blanking
bit 1 = 0 V-sync signal HIGH for
vertical sync
bit 1 = 1 V-sync signal LOW for
vertical sync
bit 2 = 0 FID signal LOW for first
field
bit 2 = 1 FID signal HIGH for first
field
47 I disable forced
field toggle
R/W bit 0 = 0 enable forced field toggle 0 If no FID polarity transitions are detected
in the input signal, then an internal toggle
of FID polarity ensures the encoding of
some frames.
bit 0 = 1 disable forced field toggle If no FID polarity transitions are detected
in the input signal, then no frames are
encoded.
ADR
HEX
M
COMMAND
NAME
R/W SIZE/POSITION PARAMETER/RANGE DEFAULT DESCRIPTION