21
Bit 0: This bit is used to reset the first 8 flip-flops [B0 thru B7] of the global register.
Writing a 0 and then a 1 will reset all 8 low bit flip-flops [B0 to B7] to 0.
Reading this bit gives the status of the GRES0 bit.
Bit 1: This bit is used to reset the second set of 8 flip-flops [B8 thru B15] of the global
register. Writing a 0 and then a 1 will reset all 8 high bit flip-flops [B8 to B15] to
0.
Reading this bit gives the status of the GRES1 bit.
Bit 2: Reserved for Future use. Write a 0 to this bit. Reading this bit is undefined.
Bit 3: Reserved for Future use. Write a 0 to this bit. Reading this bit is undefined.
Bit 4: This bit provides the status of the first 8 flip-flops of the Global Buffer Register
(GBUF). If this bit is set then one of the flip-flops in the Low Order GBUF
Register (ie: PAX0 to PAX7] was enabled. This means that one of the Opto
Isolator was set. If this bit is 0 then none of the GBUF flip-flops [Low Order] is
set.
Bit 5: This bit provides the status of the high 8 bit flip-flops of the Global Buffer
Register (GBUF). If this bit is set the one of the high 8 bit flip-flops in the GBUF
Register was enabled. This means that one of the last 8 Opto Isolator was set. If
this bit is 0 then none of the High Order GBUF flip-flops is set.
Bits 6-15: Reserved for Future use. Write a 0 to these bits. Reading these bits are
undefined.
3.3) GLCNTRL – Global Control Register (offset 4, read/write)
This register is used to enable the Mux that sets the Global Buffer to a specific IRQ. If
any one of the Opto-isolators was enabled, the pulse is set up and vectored to the
Multiplexor to a specific IRQ. This register enables and configures this line to any of 8
IRQs lines.
GLCNTRL Register (write mode)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
0 0 0 0 0 0 0 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IGATEG1
IGATEG0
IMUXG5
IMUXG4
IMUXG3
IMUXG2
IMUXG1
IMUXG0
