22
GLCNTRL Register (read mode)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
x x x x x x x x
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IGATEG1
IGATEG0
IMUXG5
IMUXG4
IMUXG3
IMUXG2
IMUXG1
IMUXG0
Bits 0-2: IMUXG0 to IMUXG3 - These bits are used to set up a global IRQ line for the
first 8 opto-isolators. The status of any opto-isolator can be checked using the
Global Register GBUF (Offset 8) using a 16 bit read.
Reading back these bits determines the status of IMUXG0 to IMUXG2 Control
lines.
IMUXG2 IMUXG1 IMUXG0 IGATE0 IRQ
0 0 0 1 10
0 0 1 1 11
0 1 0 1 12
0 1 1 1 15
1 0 0 1 2
1 0 1 1 7
1 1 0 1 5
1 1 1 1 3
Table 3.3a: Mux Table for setting IRQs
Bits 3-5: IMUXG3 to IMUXG5 - These bits are used to set up a global IRQ line for the
last 8 opto-isolators. The status of any opto-isolator can be checked using the
Global Register GBUF (Offset 8) using a 16 bit read.
Reading back these bits determines the status of the IMUXG3 to IMUXG5
Control lines.
Bits 6: IGATEG0 – This bit is used to enable/disable Global Interrupts. Setting this bit
to 1 enables one to select any one of 8 IRQ on the ISA Bus. Setting this bit to 0
disables Interrupts vectored from a pulse generated if any one of the first 8 opto-
isolators goes high.
Reading this bit determines the status of the IGATE0 bit.
Bits 7: IGATEG1 – This bit is used to enable/disable Global Interrupts. Setting this bit
to 1 enables one to select any one of 8 IRQ on the ISA Bus. Setting this bit to 0
