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Bits 2 to 4 to select 1 of 8 IRQs. Bit 2 is Address Decode A0, Bit 3 is Address
Decode A1, Bit 4 is Address Decode A2 and Gx is IGATE6.
Reading these bits determines the status of MUXP1A0 to MUXP1A2 bits.
Bits 5-7: MUXP7A0 to MUXP7A2 - These bits are used to set up an IRQ line for the
Opto-isolator 7 (PA7). Bits 5 to 7 set the IRQ selection for Opto-Isolator 7, with
IGATE7 enabling/disable interrupt support. IGATE7 must be enabled in order to
select an interrupt. Table 3.6a gives an example of the appropriate writes from
Bits 5 to 7 to select 1 of 8 IRQs. Bit 5 is Address Decode A0, Bit 6 is Address
Decode A1, Bit 7 is Address Decode A2 and Gx is IGATE7.
Reading these bits determines the status of MUXP7A0 to MUXP7A2.
Bits 8-10: MUXP8A0 to MUXP8A2 - These bits are used to set up an IRQ line for the
Opto-isolator 8 (PA8). Bits 8 to 10 sets the IRQ selection for Opto-Isolator 8,
with IGATE8 enabling/disable interrupt support. IGATE8 must be enabled in
order to select an interrupt. Table 3.6a gives an example of the appropriate writes
from Bits 8 to 10 to select 1 of 8 IRQs. Bit 8 is Address Decode A0, Bit 9 is
Address Decode A1, Bit 10 is Address Decode A2 and Gx is IGATE8.
Reading these bits determines the status of MUXP8A0 to MUXP8A2.
Bits 11-13: MUXP9A0 to MUXP9A2 - These bits are used to set up an IRQ line for the
Opto-isolator 9 (PA9). Bits 11 to 13 sets the IRQ selection for Opto-Isolator 9,
with IGATE9 enabling/disable interrupt support. IGATE9 must be enabled in
order to select an interrupt. Table 3.6a gives an example of the appropriate writes
from Bits 11 to 13 to select 1 of 8 IRQs. Bit 11 is Address Decode A0, Bit 12 is
Address Decode A1, Bit 13 is Address Decode A2 and Gx is IGATE9.
Reading these bits determines the status of MUXP4A0 to MUXP4A2.
Bits 14-15: MUXP10A0 to MUXP10A1- These bits in conjunction with bits 0 in the
IMUXP2 Register are used to set up an IRQ line for the Opto-isolator 10
(PA10). MUXP10A0 (in the IMUXP1 Register), MUXP10A1 (in the IMUXP1
Register) and MUXP10A2 (in the IMUXP2 Register) sets the IRQ selection for
Opto-Isolator 10, with IGATE10 enabling/disable interrupt support. IGATE10
must be enabled in order to select an interrupt. Table 3.7a gives an example of
the appropriate writes from Bits 14 in the IMUXP1 Register, Bit 15 in the
IMUXP1 Register and Bit 0 in the IMUXP2 Register in order to select 1 of 8
IRQs. Bit 14 is Address Decode A0 (in the IMUXP1 Register), Bit 15 (in the
IMUXP1 Register) is Address Decode A1, Bit 0 (IMUXP2 Register) is Address
Decode A2 and Gx is IGATE10.
Reading these bits determines the status of MUXP10A0 and MUXP10A1.
