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3.8) IMUXP2 – Local Mux Interrupt Control Register 3 (offset 14, read/write)
This register is used to set individual interrupts for each optically isolated input.
Effectively MUXP2 is used as address lines to map each optically isolated inputs to a
specific IRQ. If any one of the Opto-isolators was enabled, the pulse is set up and
vectored to the Decoder to a specific IRQ. This register configures this line to any of 8
IRQs lines.
IMUXP2 Register (write mode)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
MUXP15A2
MUXP15A1 MUXP15A0 MUXP14A2
MUXP14A1
MUXP14A0 MUXP13A2 MUXP13A1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MUXP13A0
MUXP12A2 MUXP12A1 MUXP12A0
MUXP11A2
MUXP11A1 MUXP11A0 MUXP10A2
IMUXP2 Register (read mode)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
MUXP15A2
MUXP15A1 MUXP15A0 MUXP14A2
MUXP14A1
MUXP14A0 MUXP13A2 MUXP13A1
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MUXP13A0
MUXP12A2 MUXP12A1 MUXP12A0
MUXP11A2
MUXP11A1 MUXP11A0 MUXP10A2
Bits 0: MUXP10A2 – This bit in conjunction with bits 14 and 15 in the IMUXP1
Register are used to set up an IRQ line for the Opto-isolator 10 (PA10).
MUXP10A0 (in the IMUXP1 Register), MUXP10A1 (in the IMUXP1 Register)
and MUXP10A2 (in the IMUXP2 Register) sets the IRQ selection for Opto-
Isolator 10, with IGATE10 enabling/disable interrupt support. IGATE10 must be
enabled in order to select an interrupt. Table 3.7a gives an example of the
appropriate writes from Bits 14 in the IMUXP1 Register, Bit 15 in the IMUXP1
Register and Bit 0 in the IMUXP2 Register in order to select 1 of 8 IRQs. Bit 14
is Address Decode A0 (in the IMUXP1 Register), Bit 15 (in the IMUXP1
Register) is Address Decode A1, Bit 0 (IMUXP2 Register) is Address Decode
A2 and Gx is IGATE10.
Reading this bit determines the status of the MUXP10A2 bit.
Bits 1-3: MUXP11A0 to MUXP11A2 - These bits are used to set up an IRQ line for the
Opto-isolator 11 (PA11). Bits 1 to 3 sets the IRQ selection for Opto-Isolator 11,
with IGATE11 enabling/disable interrupt support. IGATE11 must be enabled in
order to select an interrupt. Table 3.7a gives an example of the appropriate writes
from Bits 1 to 3 to select 1 of 8 IRQs. Bit 1 is Address Decode A0, Bit 2 is
Address Decode A1, Bit 3 is Address Decode A2 and Gx is IGATE11.
Reading these bits determines the status of MUXP11A0 to MUXP11A2 bits.
