23
disables Interrupts vectored from a pulse generated if any one of the last 8 opto-
isolators goes high.
Reading this bit determines the status of the IGATE1 bit.
Bits 8-15: Reserved for Future use. Write a 0 to these bits. Reading these bits is undefined.
3.4) IGATE – IRQ Gate Control Register (offset 6, read/write)
This register is used to enable the Gate controlling the Muxes that map each opto-isolator
input to a specific IRQ line. The MUX Control Registers (3 lines per Opto-Isolator Input)
is found in the IMUX0 (offset 10), IMUX1 (offset 12), IMUX2 (offset 14), IMUX3
(offset 16) Control Registers. For example: In the IMUX0 Control Register, bits 0 to 2 set
the IRQ Line of the 1
st
Opto-isolator. If the IGATE0 bit is 1 then a rising edge on the first
Opto-isolator will be mapped to an IRQ Line set via Bits 0 to 2 in the IMUX0 Register. If
IGATE0 bit is 0 then the IRQ Lines are effectively disconnected from the IRQ Bus. This
means that a rising edge on the first Opto-isolator will NOT be mapped to an IRQ Line set
via Bits 0 to 2 in the IMUX0 Register.
IGATE Register (write mode)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
IGATE15 IGATE14 IGATE13 IGATE12 IGATE11 IGATE10 IGATE9 IGATE8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IGATE7 IGATE6 IGATE5 IGATE4 IGATE3 IGATE2 IGATE1 IGATE0
IGATE Register (read mode)
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
IGATE15 IGATE14 IGATE13 IGATE12 IGATE11 IGATE10 IGATE9 IGATE8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IGATE7 IGATE6 IGATE5 IGATE4 IGATE3 IGATE2 IGATE1 IGATE0
Bit0: IGATE0 – This bit is used to enable/disable Interrupt support for Opto-isolator
input 0. Setting this bit to 1 enables one to select any one of 8 IRQ on the ISA
Bus. The actual IRQ selection is determined by the IMUXP0 Register (offset
10). For example, bits 0 to 2 sets the IRQ selection for Opto-Isolator 0, with
IGATE0 enabling/disable interrupt support. Table 3.4a determines the IRQ
selection. Setting the IGATE0 bit to 0 disables Interrupts support for Opto-
isolator 0.
Reading this bit determines the status of the IGATE0 bit.
