35
Bits 4-6: MUXP12A0 to MUXP12A2 - These bits are used to set up an IRQ line for the
Opto-isolator 12 (PA12). Bits 4 to 6 set the IRQ selection for Opto-Isolator 12,
with IGATE12 enabling/disable interrupt support. IGATE12 must be enabled in
order to select an interrupt. Table 3.7a gives an example of the appropriate writes
from Bits 4 to 6 to select 1 of 8 IRQs. Bit 4 is Address Decode A0, Bit 5 is
Address Decode A1, Bit 6 is Address Decode A2 and Gx is IGATE12.
Reading these bits determines the status of MUXP12A0 to MUXP12A2.
Bits 7-9: MUXP13A0 to MUXP13A2 - These bits are used to set up an IRQ line for the
Opto-isolator 13 (PA13). Bits 7 to 9 sets the IRQ selection for Opto-Isolator 13,
with IGATE13 enabling/disable interrupt support. IGATE13 must be enabled in
order to select an interrupt. Table 3.7a gives an example of the appropriate writes
from Bits 7 to 9 to select 1 of 8 IRQs. Bit 7 is Address Decode A0, Bit 8 is
Address Decode A1, Bit 9 is Address Decode A2 and Gx is IGATE13.
Reading these bits determines the status of MUXP13A0 to MUXP13A2.
Bits 10-12: MUXP14A0 to MUXP14A2 - These bits are used to set up an IRQ line for the
Opto-isolator 14 (PA14). Bits 10 to 12 sets the IRQ selection for Opto-Isolator
14, with IGATE14 enabling/disable interrupt support. IGATE14 must be enabled
in order to select an interrupt. Table 3.7a gives an example of the appropriate
writes from Bits 10 to 12 to select 1 of 8 IRQs. Bit 10 is Address Decode A0, Bit
11 is Address Decode A1, Bit 12 is Address Decode A2 and Gx is IGATE14.
Reading these bits determines the status of MUXP14A0 to MUXP14A2.
Bits 13-15: MUXP15A0 to MUXP15A2- These bits are used to set up an IRQ line for the
Opto-isolator 15 (PA15). Bits 13 to 15 set the IRQ selection for Opto-Isolator
15, with IGATE15 enabling/disable interrupt support. IGATE15 must be enabled
in order to select an interrupt. Table 3.7a gives an example of the appropriate
writes from Bits 13 to 15 to select 1 of 8 IRQs. Bit 13 is Address Decode A0, Bit
14 is Address Decode A1, Bit 15 is Address Decode A2 and Gx is IGATE15.
Reading these bits determines the status of MUXP15A0 to MUXP15A2.
