26
Reading this bit determines the status of the IGATE6 bit.
Bit7: IGATE7 – This bit is used to enable/disable Interrupt support for Opto-isolator
input 7 (PA7). Setting this bit to 1 enables one to select any one of 8 IRQs on the
ISA Bus. The actual IRQ selection is determined by the IMUXP1 Register
(offset 12). For example, bits 5 (low) to 7 (high) set the IRQ selection for Opto-
Isolator 7, with IGATE7 enabling/disabling interrupt support. Table 3.4a gives an
example of how the IRQ selection is determined. Setting the IGATE7 bit to 0
disables Interrupts support for Opto-isolator 7.
Reading this bit determines the status of the IGATE7 bit.
Bit8: IGATE8 – This bit is used to enable/disable Interrupt support for Opto-isolator
input 8 (PA8). Setting this bit to 1 enables one to select any one of 8 IRQs on the
ISA Bus. The actual IRQ selection is determined by the IMUXP1 Register
(offset 12). For example, bits 8 (low) to 10 (high) set the IRQ selection for Opto-
Isolator 8, with IGATE8 enabling/disabling interrupt support. Table 3.4a gives an
example of how the IRQ selection is determined. Setting the IGATE8 bit to 0
disables Interrupts support for Opto-isolator 8.
Reading this bit determines the status of the IGATE8 bit.
Bit9: IGATE9 – This bit is used to enable/disable Interrupt support for Opto-isolator
input 9 (PA9). Setting this bit to 1 enables one to select any one of 8 IRQs on the
ISA Bus. The actual IRQ selection is determined by the IMUXP1 Register
(offset 12). For example, bits 11 (low) to 13 (high) set the IRQ selection for
Opto-Isolator 9, with IGATE9 enabling/disabling interrupt support. Table 3.4a
gives an example of how the IRQ selection is determined. Setting the IGATE9
bit to 0 disables Interrupts support for Opto-isolator 9.
Reading this bit determines the status of the IGATE9 bit.
Bit10: IGATE10 – This bit is used to enable/disable Interrupt support for Opto-isolator
input 10 (PA10). Setting this bit to 1 enables one to select any one of 8 IRQs on
the ISA Bus. The actual IRQ selection are determined by the IMUXP1 and the
IMUXP2 Registers (offset 12 and 14). For example, bit 14 (A0) in the IMUXP1
Register is the low bit in the decoder and Bit0 in the IMUXP2 Register is the
high bit in the decoder. These bits set the IRQ selection for Opto-Isolator 10,
with IGATE10 enabling/disabling interrupt support. Table 3.4b gives an example
of how the IRQ selection is determined. Setting the IGATE10 bit to 0 disables
Interrupts support for Opto-isolator 10.
Reading this bit determines the status of the IGATE10 bit.
