25
Bit4: IGATE4 – This bit is used to enable/disable Interrupt support for Opto-isolator
input 4 (PA4). Setting this bit to 1 enables one to select any one of 8 IRQs on the
ISA Bus. The actual IRQ selection is determined by the IMUXP0 Register
(offset 10). For example, bits 12 (low) to 14 (high) set the IRQ selection for
Opto-Isolator 4, with IGATE4 enabling/disabling interrupt support. Table 3.4a
gives an example of how the IRQ selection is determined. Setting the IGATE4
bit to 0 disables Interrupts support for Opto-isolator 4.
Reading this bit determines the status of the IGATE4 bit.
Bit5: IGATE5 – This bit is used to enable/disable Interrupt support for Opto-isolator
input 5 (PA5). Setting this bit to 1 enables one to select any one of 8 IRQs on the
ISA Bus. The actual IRQ selection are determined by the IMUXP0 and IMUXP1
Registers (offset 12). For example, bit 15 (A0) in the IMUXP0 Register is the
low bit in the decoder and Bit1 in the IMUXP1 Register is the high bit in the
decoder. These bits set the IRQ selection for Opto-Isolator 5, with IGATE5
enabling/disabling interrupt support. Table 3.4b gives an example of how the
IRQ selection is determined. Setting the IGATE5 bit to 0 disables Interrupts
support for Opto-isolator 5.
Reading this bit determines the status of the IGATE5 bit.
1IMUX1 1IMUX0 0IMUX15 IGATE5 IRQ
Bit 1
Bit 0 Bit 15 Bit 5 IRQ
0 0 0 1 10
0 0 1 1 11
0 1 0 1 12
0 1 1 1 15
1 0 0 1 2
1 0 1 1 7
1 1 0 1 5
1 1 1 1 3
Table 3.4b: Mux Table for setting IRQs on Opto-isolator 6
Bit6: IGATE6 – This bit is used to enable/disable Interrupt support for Opto-isolator
input 6 (PA6). Setting this bit to 1 enables one to select any one of 8 IRQs on the
ISA Bus. The actual IRQ selection is determined by the IMUXP1 Register
(offset 12). For example, bits 2 (low) to 4 (high) set the IRQ selection for Opto-
Isolator 6, with IGATE6 enabling/disabling interrupt support. Table 3.4a gives an
example of how the IRQ selection is determined. Setting the IGATE6 bit to 0
disables Interrupts support for Opto-isolator 6.
