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5-4
Programming Commands
Common Commands
<integer>
is a mask from 0 to 255.
Description
The event status enable register contains a mask value for the bits to be
enabled in the event status register. A bit set to one (1) in the event status
enable register enables the corresponding bit in the event status register to
set the event summary bit in the status byte register. A zero (0) disables the
bit. Refer to the following table for information about the event status enable
register bits, bit weights, and what each bit masks. The event status enable
register is cleared at power-on. The *RST and *CLS commands do not change
the register. The *ESE? query returns the value of the event status enable reg-
ister.
Query Response
<integer>
is a mask from 0 to 255.
Example
OUTPUT 720;”*ESE 32”
In this example, the *ESE 32 command enables CME (event summary bit) bit
5 of the event status enable register. Therefore, when an incorrect program-
ming command is received, the CME (command error bit) in the status byte
register is set.
Table 5-2. Event Status Enable Register
Bit
a
a. A high enables the event status register bit.
Bit Weight Enables
7 128 PON – Power On
6 64 Not Used
5 32 CME – Command Error
4 16 EXE – Execution Error
3 8 DDE – Device Dependent Error
2 4 QYE – Query Error
1 2 Not Used
0 1 OPC – Operation Complete