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BIOS Intel® Server Board SE7501WV2 TPS
Revision 1.0
Intel reference number C25653-001
114
6.36 System Limit Error
The BMC monitors system operational limits. It manages the A/D converter, defining voltage
and temperature limits as well as fan sensors and chassis intrusion. Any sensor values outside
of specified limits are fully handled by BMC. The BIOS does not generate an SMI to the host
processor for these types of system events.
Refer to the SE7501WV2 Server Management External Architecture Specification for details on
various sensors and how they are managed.
6.37 Boot Event
The BIOS downloads the system date and time to the BMC during POST and logs a boot event
in the system event log. Software applications that parse the event log should not treat this boot
event as an error.
6.38 Fault Resilient Booting (FRB)
The BIOS and firmware provides a feature to guarantee that the system boots, even if one or
more processors fail during POST. The BMC contains two watchdog timers that can be
configured to reset the system upon time-out.
6.38.1 FRB3
FRB3 refers to the FRB algorithm that detects whether the BSP is healthy enough to run BIOS
at all. The BMC starts the FRB3 timer when the system is powered up or hard reset. The BIOS
stops this timer in the power-on self test (POST) by asserting the FRB3 timer halt signal to the
BMC. This requires that the BSP actually runs BIOS code. If the timer is not stopped within 5
seconds, and it expires, the BMC disables the BSP, logs an FRB3 error event, chooses another
BSP (from the set of non-failed processors), and resets the system. FRB3 provides a check to
verify that the selected BSP is not dead on start up and can actually run code. This process
repeats until either the system boots without an FRB3 timeout, or all of the remaining
processors have been disabled. At this point, if all the processors have been disabled, the BMC
will attempt to boot the system on one processor at a time, irrespective of processor error
history. This is called desperation mode.
6.38.2 FRB2
FRB2 refers to the level of FRB in which the BIOS uses the BMC watchdog timer to back up its
operation during POST. The BIOS configures the watchdog timer for approximately 6-10
minutes indicating that the BIOS is using the timer for the FRB2 phase of operation.
After BIOS has identified the BSP and saved that information, it will then check to see if the
watchdog timer expired on the previous boot. If so, it will store the Time Out Reason bits in a
fixed CMOS location (token name = cmosWDTimerFailReason) for applications or a User
Binary to examine and act upon. Next, it sets the watchdog timer FRB2 timer use bit, loads the
watchdog timer with the new timeout interval, and disables FRB3 using the FRB3 timer halt
signal. This sequence ensures that no gap exists in watchdog timer coverage between FRB3
and FRB2.
Note: FRB2 is not supported when the BIOS is in Recovery Mode.