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Configuration and Initialization Intel® Server Board SE7501WV2 TPS
Revision 1.0
Intel reference number C25653-001
38
4. Configuration and Initialization
This section describes the configuration and initialization of various baseboard sub-systems as
implemented on the SE7501WV2 server board.
4.1.1 Main Memory
All installed memory greater than 1 MB is mapped to local main memory, up to the top of
physical memory, which is located at 12 GB. Memory between 1 MB to 15 MB is considered
standard ISA extended memory. 1 MB of memory starting at 15 MB can be optionally mapped
to the PCI bus memory space.
The remainder of this space, up to 12 GB, is always mapped to main memory, unless Extended
SMRAM is used, which limits the top of memory to 256 MB.
4.1.1.1 PCI Memory Space
Memory addresses below the 4 GB range are mapped to the PCI bus. This region is divided into
three sections: High BIOS, APIC Configuration Space, and General-purpose PCI Memory. The
General-purpose PCI Memory area is typically used for memory-mapped I/O to PCI devices.
The memory address space for each device is set using PCI configuration registers.
4.1.1.2 High BIOS
The top 2 MB of Extended Memory is reserved for the system BIOS, extended BIOS for PCI
devices, and A20 aliasing by the system BIOS. The Intel® Xeon™ processor begins executing
from the high BIOS region after reset.
4.1.1.3 I/O APIC Configuration Space
A 64 KB block located 20 MB below 4 GB is reserved for the I/O APIC configuration space.
4.1.1.4 Extended Xeon Processor Region (above 4GB)
An Intel
®
Xeon™ processor-based system can have up to 64 GB of addressable memory. The
BIOS uses the Extended Addressing mechanism to use the address ranges.
4.1.2 Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be “shadowed” into
main memory. This is typically done to allow ROM code to execute more rapidly out of RAM.
ROM is designated read-only during the copy process while RAM at the same address is
designated write-only. After copying, the RAM is designated read-only and the ROM is
designated write-only (shadowed). Processor bus transactions are routed accordingly.
Transactions originated from the PCI bus or ISA masters and targeted at the shadowed memory
block will not appear on the processor’s bus.