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Intel® Server Board SE7501WV2 TPS BIOS
Revision 1.0
Intel reference number C25653-001
115
If the watchdog timer expires while the watchdog use bit is set to FRB2, the BMC logs a
watchdog expiration event showing an FRB2 timeout (if so configured). It then hard resets the
system, assuming Reset was selected as the watchdog timeout action.
The BIOS is responsible for disabling the FRB2 timeout before initiating the option ROM scan,
prior to displaying a request for a Boot Password or prior to an Extensive Memory Test. The
BIOS will re-enable the FRB2 timer after the Extensive Memory Test. The BIOS will provide a
user-configurable option to change the FRB2 response behavior. These 4 options shall be:
• Disable on FRB2
• Never Disable
• Disable after 3 consecutive FRB2s
• Disable FRB2 timer
The option of “Disable on FRB2” will do the following. If the FRB2 timer expires (i.e., a
processor has failed FRB2), the BMC resets the system. As part of its normal operation, the
BIOS obtains the watchdog expiration status from the BMC. If this status shows an expiration of
the FRB2 timer, the BIOS logs an FRB2 event with the event data being the last Port 80h code
issued in the previous boot. The BIOS also issues a Set Processor State command to the
BMC, indicating an FRB2 failure and telling it to disable the BSP and reset the system. The
BMC then disables the processor that failed FRB2 and resets the system, causing a different
processor to become the BSP.
The option of “Never Disable” will perform all the same functions as “Disable on FRB2” with the
exception that the BIOS will not send a Set Processor State command to the BMC. The BIOS
will still log the FRB2 event in the SEL.
The option of “Disable after 3 consecutive FRB2s” will perform all the same functions as
“Disable on FRB2” with the following exception. The BIOS will maintain a failure history of the
successive boots. If the same BSP fails 3 consecutive boots with an FRB2, the processor
would then be disabled. If the system successfully boots to a BSP, the failure history
maintained by the BIOS should be cleared.
The option of “Disable FRB2 Timer” will cause the BIOS to not start the FRB2 timer in the BMC
during POST. If this option is selected, the system will have no FRB protection after the FRB3
timer is disabled. The BIOS and BMC implement additional safeguards to detect and disable the
application processors (AP) in a multiprocessor system. If an AP fails to complete initialization
within a certain time, it is assumed to be nonfunctional. If the BIOS detects that an AP is
nonfunctional, it requests the BMC to disable that processor. When the BMC disables the
processor and generates a system reset, the BIOS will not see the bad processor in the next
boot cycle. The failing AP is not listed in the MP table (refer to the Multi-Processor Specification,
Rev. 1.4), nor in the ACPI APIC tables, and is invisible to the operating system.
All the failures (late POST, OS Boot, FRB-3, FRB-2, and AP failures) including the failing
processor are recorded into the System Event Log. However, the user should be aware that if
the setup option for error logging is disabled, these failures are not recorded. The FRB-3 failure
is recorded automatically by the BMC while the late POST, OS Boot, FRB-2, and AP failures are
logged to the SEL by the BIOS. In the case of an FRB-2 failure, some systems will log additional
information into the OEM data byte fields of the SEL entry. This additional data indicates the last