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Functional Architecture Intel® Server Board SE7501WV2 TPS
Revision 1.0
Intel reference number C25653-001
30
• Support for Zero Channel RAID (ZCR) or M-ROMB that allows the on board SCSI
controller to be “hidden” from system and used by the RAID processor on the add-in card.
The BIOS is responsible for setting the bus speed of the P64-C. The bus speed will always be
set up to run at the speed of the slowest card installed.
Table 5. P64-C Speeds
Configuration
Intel
®
Server Chassis SR1300
(Bus C with AIC7902 SCSI down
and 1 Slot Riser)
Intel
®
Server Chassis SR2300
(Bus C with AIC7902 SCSI
down and 3 Slot Riser)
0 Adapter Cards installed
and on board device
enabled
PCI-X 100 PCI-X 100
1 Adapter Cards installed
and on board device
enabled
PCI-X 100 PCI-X 100
2 Adapter Cards installed
and on board device
enabled
N/A PCI-X 100
3 Adapter Cards installed
and on board device
enabled
N/A PCI-X 64/66
1 Adapter Cards installed
and on board device
disabled
PCI-X 64/100 PCI-X 64/100
2 Adapter Cards installed
and on board device
disabled
N/A PCI-X 64/100
3 Adapter Cards installed
and on board device
disabled
N/A PCI-X 64/66
3.2.4 ICH3-S
The ICH3-S is a multi-function device, housed in a 421-pin BGA device, providing a HI 1.5 to
PCI bridge, a PCI IDE interface, a PCI USB controller, and a power management controller.
Each function within the ICH3-S has its own set of configuration registers. Once configured,
each appears to the system as a distinct hardware controller sharing the same PCI bus
interface.
On the SE7501WV2 server board, the primary role of the ICH3-S is to provide the gateway to all
PC-compatible I/O devices and features. The SE7501WV2 server board uses the following
ICH3-S features:
• PCI bus interface
• LPC bus interface
• IDE interface, with Ultra DMA 100 capability
• Universal Serial Bus (USB) interface
• PC-compatible timer/counter and DMA controllers