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Configuration and Initialization Intel® Server Board SE7501WV2 TPS
Revision 1.0
Intel reference number C25653-001
40
Figure 7. CONFIG_ADDRES Register
4.3.1.1 Bus Number
PCI configuration space protocol requires that all PCI buses in a system be assigned a bus
number. Furthermore, bus numbers must be assigned in ascending order within hierarchical
buses. Each PCI bridge has registers containing its PCI bus number and subordinate PCI bus
number, which must be loaded by POST code. The Subordinate PCI bus number is the bus
number of the last hierarchical PCI bus under the current bridge. The PCI bus number and the
Subordinate PCI bus number are the same in the last hierarchical bridge.
4.3.1.2 Device Number and IDSEL Mapping
Each device under a PCI bridge has its IDSEL input connected to one bit out of the PCI bus
address/data signals AD[31::11] for the PCI bus. Each IDSEL-mapped AD bit acts as a chip
select for each device on PCI. The host bridge responds to a unique PCI device ID value, that
along with the bus number, cause the assertion of IDSEL for a particular device during
configuration cycles. The following table shows the correspondence between IDSEL values and
PCI device numbers for the PCI bus. The lower 5-bits of the device number are used in
CONFIG_ADDRESS bits [15::11].
Table 9. PCIdevice IDs
Device Description Bus Device ID
(Hex)
North Bridge (MCH) 0 00
ICH3 P2P Bridge 1 1E
ICH3 USB 1 1D
ICH3 IDE 1 1F
Video 1 0C
RIDE 1 02
00
Register
017810 11 15 16 23 24 30 31
Functio
Device Bus Number Reserved
Enable bit (‘1’ = enabled, ‘0’ = disabled)