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Intel® Server Board SE7501WV2 TPS BIOS
Revision 1.0
Intel reference number C25653-001
131
• MP table header
• Processor entries
• PCI bus entries
• I/O APIC entries
• Local interrupt entries
• System address space-mapping entries
• Bus hierarchy descriptor
• Compatibility bus address space modifier entries
6.45.2 Multiple Processor Support
IA-32 processors have a microcode-based MP initialization protocol. On reset, all of the
processors compete to become the bootstrap processor (BSP). If a serious error is detected
during a Built-in Self-Test (BIST), the processor does not participate in the initialization protocol.
A single processor that successfully passes BIST is automatically selected by the hardware as
the BSP and starts executing from the reset vector (F000:FFF0h). A processor that does not
perform the role of BSP is referred to as an application processor (AP).
The BSP is responsible for executing POST and preparing the machine to boot the operating
system. The system BIOS performs several other tasks in addition to those required for MPS
support, as described in Revision 1.4 of the MP specification. These tasks are part of the fault
resilient booting algorithm. At the time of booting, the system is in virtual wire mode and only the
BSP is programmed to accept local interrupts (INTR driven by programmable interrupt controller
(PIC) and non-maskable interrupt (NMI)). For platforms with a single processor configuration,
the system is put in the virtual wire mode, which uses the local APIC of the processor.
As a part of the boot process, the BSP wakes each AP. When awakened, the AP programs its
memory type range registers (MTRRs) to be identical to those of the BSP. All APs execute a halt
instruction with their local interrupts disabled. The server management module (SMM) handler
expects all processors to respond to an SMI. To ensure that an AP can respond to an SMI, any
agent that wakes an AP must ensure that the AP is left in the Halt State, not the “wait for startup
IPI” state. The waking agent must also ensure that the code segment containing the halt code
executed by an AP is protected and does not get overwritten. Failure to comply with these
guidelines results in a system hang during the next SMI.
6.45.3
Mixed Processor Support
The SE7501WV2 BIOS supports different versions of processors of various clock frequencies
without changes to the BIOS, but only across different system configurations.
All installed
processors will be configured to run at the same frequency. (For example, the bus frequency of
all processors must be identical. If the core frequency of the processors differs, the BIOS will
configure both processors to run at the core speed of the slower processor.)
For best
performance, all processors must be of the same revision.
Mixing processor families is considered an error condition. Mixing processors with different
cache sizes results in a warning message. Mixing steppings (within the same family) is
supported as long as the processors are + one or – one stepping within each other, only
identical processors are tested by Intel.
The BIOS setup reports the type, cache size and speed of all detected and enabled processors.