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Intel® Server Board SE7501WV2 TPS Configuration and Initialization
Revision 1.0
Intel reference number C25653-001
51
4.11.1 Legacy Interrupt Routing
For PC-compatible mode, the ICH3-S provides two 82C59-compatible interrupt controllers. The
two controllers are cascaded with interrupt levels 8-15 entering on level 2 of the primary
interrupt controller (standard PC configuration). A single interrupt signal is presented to the
processors, to which only one processor will respond for servicing.
4.11.1.1 Legacy Interrupt Sources
The following table recommends the logical interrupt mapping of interrupt sources on the
SE7501WV2 server board. The actual interrupt map is defined using configuration registers in the
ICH3-S.
Table 19. Interrupt Definitions
ISA Interrupt Description
INTR Processor interrupt.
NMI NMI to processor.
IRQ1 Keyboard interrupt.
IRQ3 Serial port A or B interrupt from SIO device, user-configurable.
IRQ4 Serial port A or B interrupt from SIO device, user-configurable.
IRQ5
IRQ6 Floppy disk.
IRQ7
IRQ8_L Active low RTC interrupt.
IRQ9
IRQ10
IRQ11
IRQ12 Mouse interrupt.
IRQ14 Compatibility IDE interrupt from primary channel IDE devices 0 and 1.
IRQ15
SMI* System Management Interrupt. General purpose indicator sourced by the ICH3-S and BMC to the
processors.
SCI* System Control Interrupt. Used by system to change sleep states and other system level type
functions.
4.11.2 Serialized IRQ Support
The SE7501WV2 server board supports a serialized interrupt delivery mechanism. Serialized
IRQs (SERIRQ) consist of a start frame, a minimum of 17 IRQ / data channels, and a stop
frame. Any slave device in the quiet mode may initiate the start frame. While in the continuous
mode, the start frame is initiated by the host controller.
4.11.3 APIC Interrupt Routing
For APIC mode, the SE7501WV2 server board interrupt architecture incorporates three Intel
®
APIC devices to manage and broadcast interrupts to local APICs in each processor. One of the
APICs is located in the ICH3-S and the other two APICs are in the P64H2 (one for each PCI