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Functional Architecture Intel® Server Board SE7501WV2
Revision 1.0
Intel reference number C25653-001
28
• The ICH3-S provides a 32-bit/33-MHz PCI bus hereafter called P32-A.
• The P64H2 provides two independent 64-bit, 133-MHz PCI-X buses hereafter called
P64-B, and P64-C.
This independent bus structure allows all three PCI buses to operate concurrently.
3.2.1 MCH Memory Architecture
The MCH supports a 144-bit wide Memory Sub-system that can support a maximum of 12 GB
(using 2 GB DIMMs). This configuration needs external registers for buffering the memory
address and control signals. In this configuration the MCH supports six DDR266 compliant
registered stacked DIMMs for a maximum of 12 GB. (DDR200 DIMMs are supported when
400MHz processors are used.) The six chip selects are registered inside the MCH and need no
external registers for chip selects.
The memory interface runs at 266 MHz. (200 MHz when DDR-200 modules and 400 MHz
processors are used.) The memory interface supports a 144-bit wide memory array. It uses
fifteen address lines (BA[1:0] and MA[12:0]) and supports 64 Mb, 128 Mb, 256 Mb, 512 Mb
DRAM densities. The DDR DIMM interface supports memory scrubbing, single-bit error
correction, and multiple bit error detection as well as the Intel® Single Device Data Correction
features.
3.2.1.1 DDR Configurations
The DDR interface supports up to 12GB of main memory and supports single- and double-density
DIMMs.
3.2.2 MCH North Bridge
The E7501 MCH North Bridge (MCH) is a 1005 ball FC-BGA device and uses the proven
components of previous generations like the Intel
®
Pentium
®
4 bus interface unit, the Hub
Interface unit, and the DDR memory interface unit. In addition, the MCH incorporates a Hub
Interface (HI). The hub interface enables the MCH to directly interface with the P64H2. The
MCH also increases the main memory interface bandwidth and maximum memory configuration
with a 144-bit wide memory interface.
The MCH integrates three main functions:
• An integrated high performance main memory subsystem.
• An HI 2.0 bus interface that provides a high-performance data flow path between the
host bus and the I/O subsystem.
• A HI 1.5 bus which provides an interface to the ICH3-S (South Bridge).
Other features provided by the MCH include the following:
• Full support of ECC on the memory bus
• Full support of the Intel® Single Device Data Correction features.
• Twelve deep in-order queue
• Full support of registered DDR266 ECC DIMMs (DDR200 DIMMs when 400MHz
processors are used)
• Support for 12 GB of DDR memory
• Memory scrubbing