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SE7501WV2 ACPI Implementation Intel® Server Board SE7501WV2 TPS
Revision 1.0
Intel reference number C25653-001
136
7. SE7501WV2 ACPI Implementation
7.1 ACPI
An ACPI aware operating system (OS) generates an SMI to request that the system be
switched into ACPI mode. The BIOS responds by sending the appropriate command to the
BMC to enable ACPI mode. The system automatically returns to legacy mode upon hard reset
or power-on reset.
The SE7501WV2 platform supports S0, S1, S4, and S5 states. When the system is operating in
ACPI mode, the operating system retains control of the system and operating system policy
determines the entry methods and wakeup sources for each sleep state. Sleep entry and
wakeup event capabilities are provided by the hardware but are enabled by the operating
system.
S0 Sleep State
The S0 sleep state is when everything is on. This is the state that no sleep is
enabled.
S1 Sleep State
The S1 sleep state is a low wake-up latency sleep state. In this state, no
system context is lost (Processor or chip set). The system context is
maintained by the hardware.
S4 Sleep State
The S4 Non-Volatile Sleep state (NVS) is a special global system state that
allows system context to be saved and restored (relatively slowly) when
power is lost to the baseboard. If the system has been commanded to enter
the S4 sleep state, the operating system will write the system context to a
non-volatile storage file and leave appropriate context markers.
S5 Sleep State
The S5 sleep state is similar to the S4 sleep state except the operating
system does not save any context nor enable any devices to wake the
system. The system is in the “soft” off state and requires a complete boot
when awakened.
7.1.1 Front Panel Switches
The SE7501WV2 server board supports up to four front panel buttons (via anyone of three
different front panel interface connectors):
• Power button/ sleep button
• Reset button
• System identification button
• NMI button
The power button input (FP_PWR_BTN*) on the SE7501WV2 design is a request that is
forwarded by the BMC to the power state functions in the National* PC87417 Super I/O chip.
The power button state is monitored by the BMC. It does not directly control power on the power
supply.